Fin Transistor Silicide Layer for Memory Cell Resistance
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Solution Overview
Problem
The existing techniques for forming a silicide layer in fin transistors, particularly in non-volatile memory cells, face challenges in improving electron injection efficiency and reducing rewriting time, with conventional silicide layers only covering the surface and not effectively lowering the resistance of the source and drain regions.
Innovation Solution
A full-silicide layer is formed on the fin, covering both the surface and internal parts, with a silicide layer sandwiched between the source and drain regions, using a nickel silicide layer and platinum, and carbon or nitrogen introduction to suppress overgrowth, thereby reducing the resistance and enhancing electron injection efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional silicide layer is formed only on the surface of the fin, then the manufacturing process is simpler, but the resistance of the source and drain regions cannot be effectively lowered and electron injection efficiency is poor
Solution Approach 1:
The silicide layer is extended from a two-dimensional surface layer into the third dimension by forming it within the internal parts of the fin structure. This vertical penetration into the fin allows the silicide layer to reach the source and drain regions more effectively, reducing their resistance and improving electron injection efficiency without significantly complicating the manufacturing process.
2Reliability
If the silicide layer is formed to cover internal parts of the fin, then the resistance of source and drain regions is reduced, but the silicide layer may overgrow and affect adjacent structures
Solution Approach 1:
Different regions of the fin structure are treated differently during silicide formation. The silicide layer is selectively formed in specific zones (source and drain regions) while controlling its growth to prevent encroachment into the channel region and adjacent structures. This localized treatment achieves resistance reduction without harmful overgrowth.
Solution Approach 2:
The gate electrode structure serves as a physical barrier that prevents silicide layer overgrowth into the channel region before the harmful effect can occur. By positioning the gate electrode appropriately, the invention proactively blocks the potential overgrowth of silicide, maintaining clear boundaries between different functional regions.
3Loss of time
If a full-silicide layer is formed with carbon or nitrogen introduction, then the rewriting time is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
Carbon or nitrogen atoms are introduced into the silicide layer to modify its electrical and structural parameters. This compositional change enhances the electron injection efficiency and reduces rewriting time. The modification is achieved through controlled incorporation of these elements during the silicide formation process, balancing performance improvement with manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the rewriting time for memory cells by improving electron injection efficiency and lowering the resistance of the source and drain regions, enhancing the performance and reliability of semiconductor devices.
Implementation Method 1
a first silicide layer forming a part of a first source region and a second silicide layer forming a part of a first drain region which are formed in a manner that the first part is sandwiched therebetween in the first direction
Implementation Method 2
carbon or nitrogen introduction to suppress overgrowth
Data Source
AI summary
A memory gate electrode and a control gate electrode are formed to cover a fin projecting from the upper surface of a semiconductor substrate. A part of the fin which is covered by the memory gate electrode and the control gate electrode is sandwiched by a silicide layer as a part of a source region and a drain region of a memory cell. This silicide layer is formed as a silicide layer.