Fin Transistor Stacked Gate Reduces GIDL Leakage
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Solution Overview
Problem
Fin channel transistors in semiconductor devices experience increased leakage current due to gate-induced drain leakage (GIDL) phenomenon, degrading data retention and refresh characteristics, especially in DRAM cells.
Innovation Solution
A semiconductor device with a fin transistor featuring a stacked gate electrode structure comprising a p+ poly silicon layer and a p+ poly silicon germanium (Si1-xGex) layer, where 0<x<1, to reduce GIDL effects and enhance refresh characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p+ polysilicon layer is used as the lower gate electrode, then the gate control capability is improved, but gate induced drain leakage (GIDL) increases due to the large work function difference with p- silicon substrate
Solution Approach 1:
The patent changes the work function parameter of the lower gate electrode by replacing p+ polysilicon with p+ polysilicon germanium alloy. The germanium content is optimized to achieve a work function closer to that of the p- silicon substrate, thereby reducing the work function difference and minimizing GIDL while maintaining adequate gate control capability.
Solution Approach 2:
The patent uses a composite material approach by employing polysilicon germanium alloy instead of pure polysilicon. The composite structure combines silicon and germanium in specific proportions to achieve the desired electrical characteristics, particularly an optimized work function that reduces GIDL effects while preserving gate control.
2Reliability
If the fin channel structure is used to increase surface area, then short channel effects are reduced, but manufacturing complexity increases
Solution Approach 1:
The gate electrode is segmented into two distinct parts: an upper gate electrode and a lower gate electrode. The lower gate electrode is selectively formed only in regions where fin channels are present, while the upper gate electrode spans across both fin channel regions and isolation regions. This segmentation allows the fin channel structure to provide excellent short channel control while simplifying the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stacked gate structure with a p+ poly silicon germanium layer improves data retention and refresh characteristics by reducing leakage current, thereby enhancing the performance of semiconductor devices like DRAM cells.
Implementation Method 1
A work function of the p+ polysilicon layer is larger than that of a p− silicon substrate. Using a DRAM cell as an example, when there is a binary '1' voltage in the drain region while the fin channel transistor is turned off, a leakage current in the drain region is increased due to a gate induced drain leakage ('GIDL') phenomenon.
Data Source
AI summary
A semiconductor device comprises a fin-type active region defined by a semiconductor substrate having a device isolation structure, a recess formed over the fin-type active region, and a gate electrode including a silicon germanium (Si1-xGex) layer for fill the recess (where 0<X<1 and X is a Ge mole fraction).