Fin Trim Isolation for Self-Aligned Sub-10 nm FinFET Gates
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Solution Overview
Problem
The scaling of integrated circuits to sub-10 nanometer nodes faces challenges due to variability in conventional fabrication processes, limiting the extension of these processes into the 10 nanometer node or smaller ranges, necessitating new methodologies or integration of new technologies to optimize device performance.
Innovation Solution
The implementation of pitch quartering and fin trim isolation approaches in semiconductor fabrication, which involve advanced patterning techniques such as spacer-based double-patterning and fin trim processes, to achieve tighter pitch and improved transistor density while maintaining desirable fin stress for enhanced carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node or smaller
Solution Approach 1:
The patent applies pitch quartering which divides the patterning process into multiple stages: first forming mandrels at a relaxed pitch, then creating spacers around mandrels, removing mandrels, and repeating the process to achieve 4x pitch reduction. This segmentation transforms a single complex high-precision step into multiple manageable steps, each operating at relaxed precision requirements while achieving cumulative sub-10 nanometer precision.
Solution Approach 2:
The fin trim isolation process performs preliminary actions by forming isolation regions before final gate patterning. The method pre-defines fin depth variations at different locations using selective etching and fill processes, ensuring that when gates are later formed, the fins are already properly isolated and sized, eliminating the need for dummy gates and reducing subsequent process complexity.
2Productivity
If transistor density is increased through scaling, then productivity improves, but manufacturing precision requirements become more stringent
Solution Approach 1:
The spacer-based patterning process is self-aligning: spacers automatically form at precise locations relative to mandrels through conformal deposition, eliminating the need for separate alignment steps. The fin trim isolation similarly uses self-aligned etching where the isolation regions are defined by the fin structures themselves, ensuring precise feature size control without adding process complexity.
3Manufacturing precision
If fin trim isolation is implemented, then manufacturing precision improves for fin alignment, but device complexity increases
Solution Approach 1:
The patent merges the fin isolation process with the fin formation process itself. The same selective etching and fill operations that create the fin trim isolation are integrated into the existing pitch quartering sequence, rather than being separate additional steps. This merging achieves precise fin alignment while minimizing the increase in overall process complexity.
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.