Fin Trim Isolation in 10 nm IC Fabrication for Precise Fin Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling of features in integrated circuits to the 10 nanometer node and beyond is hindered by variability in conventional fabrication processes, limiting the ability to further miniaturize and optimize device performance.
Innovation Solution
The implementation of pitch quartering and fin trim isolation techniques, combined with advanced doping methods and trench isolation structures, to enhance transistor density and maintain desirable fin stress for improved carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to variability at 10 nanometer node and smaller
Solution Approach 1:
The patent applies pitch quartering which divides the patterning process into multiple stages, creating mandrels and spacers in sequential steps to achieve finer feature sizes. This segmentation enables precise control of fin dimensions and spacing that cannot be achieved with conventional single-step lithography at 10 nanometer node and below
Solution Approach 2:
The patent implements fin trim isolation that creates different fin depths and isolation characteristics in different regions of the substrate. By selectively removing portions of fins and applying localized isolation structures, the process achieves variable fin properties across the wafer to optimize device performance while maintaining manufacturing control
2Productivity
If feature size is reduced to increase device density, then productivity is improved, but manufacturing precision deteriorates due to process variability
Solution Approach 1:
The patent forms isolation structures before final fin patterning and trimming operations. By pre-establishing the isolation framework, subsequent fin formation and trimming processes can proceed with better control over final fin dimensions and positions, reducing variability even as feature sizes shrink to increase device density
Solution Approach 2:
The self-aligned spacer formation process uses the mandrels themselves to define the position of spacers, eliminating the need for separate alignment steps. This self-service mechanism inherently maintains precision as features are reduced in size, since each feature's position is determined by its neighbor rather than by global alignment
3Manufacturing precision
If pitch quartering and fin trim isolation techniques are implemented, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The pitch quartering process nests multiple patterning cycles within each other, where spacers are formed around mandrels, then mandrels are removed and new spacers are formed around the first spacers. This nested structure of process steps systematically builds complexity while maintaining precision through repeated application of the same fundamental formation/removal cycle
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional fin structures with varying depths. By adding the vertical dimension through selective fin removal and differential isolation, the process achieves precise fin control that cannot be obtained through planar techniques alone, justifying the increased process complexity
4Reliability
If advanced doping methods and trench isolation structures are used, then transistor performance is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent applies different doping concentrations and isolation structures to different regions of the substrate based on device requirements. By locally optimizing fin properties, doping profiles, and isolation characteristics, the process achieves superior transistor performance across diverse device types while managing manufacturing complexity through regional specialization
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.