Fin Tunneling Field Effect Transistor Gate Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional planar tunneling field effect transistors (TFETs) face limitations in on-state current and control due to their two-dimensional structure, which becomes less effective as device dimensions shrink, leading to increased subthreshold current leakage and reduced gate control over the channel.
Innovation Solution
A fin tunneling field effect transistor (TFET) with a three-dimensional structure is developed, featuring a semiconductor body with a gate disposed on multiple sides of the channel, using semiconductor materials with high electron and hole mobility and narrow bandgap, and a complementary design with N-type and P-type fin TFETs to enhance on-state current and control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional planar TFET structure is used, then the device can be manufactured with simpler processes, but the on-state current is limited and gate control over the channel is reduced
Solution Approach 1:
The patent transitions from a two-dimensional planar TFET structure to a three-dimensional FinFET structure. The gate is wrapped around the channel in a fin configuration, providing control from multiple sides (top, front, and back) rather than just one side. This dimensional change increases the effective gate control area and enhances the on-state current while maintaining manufacturability through established FinFET fabrication processes.
2Productivity
If device dimensions are reduced to sub-micrometer or nanometer scale, then circuit integration and power savings are improved, but short channel effect and subthreshold current leakage increase
Solution Approach 1:
By adopting a three-dimensional FinFET structure, the gate wraps around the channel from multiple directions, providing superior electrostatic control over the channel compared to planar structures. This enhanced control allows the device to maintain low subthreshold current leakage even when scaled to sub-micrometer and nanometer dimensions, enabling continued circuit integration improvements without suffering from short channel effects.
Solution Approach 2:
The gate structure is nested around the channel in a fin configuration, with the gate material surrounding the channel from multiple sides. This nested arrangement provides enhanced electrostatic control and allows the device to maintain effective gate control at reduced dimensions, mitigating short channel effects and subthreshold leakage.
3Device complexity
If a conventional planar TFET structure is used, then the device structure is simpler, but the tunneling area and probabilistic tunneling are limited
Solution Approach 1:
The FinFET structure creates a three-dimensional fin-like channel that extends vertically, increasing the effective tunneling area compared to a planar structure. The gate wraps around this fin structure, providing control from multiple sides and increasing the active tunneling region. This dimensional change enhances probabilistic tunneling without excessively increasing structural complexity, as the fin structure can be formed using standard semiconductor fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The fin TFET achieves higher on-state current and improved gate control, reducing subthreshold current leakage and enhancing circuit performance by increasing the tunneling area and probabilistic tunneling, thereby overcoming the limitations of conventional planar TFETs.
Implementation Method 1
a positive bias is applied to the gate (VG>0). This causes the potential of the channel to decrease, and the barrier layer between the source and channel to become thinner. Subsequently, electrons may tunnel from the source to the channel
Implementation Method 2
electrons may tunnel from the source to the channel, and then drift to the drain under the influence of the electric field
Implementation Method 3
The dopant types in the source and drain of the TFET are different from those in a conventional MOSFET. For example, in the n-type TFET (nTFET) shown in FIG. 1A, the N+ doped region is the drain and the P+ doped region is the source.
Data Source
AI summary
A fin tunneling field effect transistor (TFET) is disclosed. The fin TFET includes a semiconductor body extending in a first direction on a substrate, wherein the semiconductor body constitutes a channel of the fin TFET. The fin TFET also includes a source and a drain disposed at opposite ends of the semiconductor body, wherein the source is doped with a first dopant type and the drain is doped with a second dopant type, and the first dopant type is different from the second dopant type. The fin TFET further includes a gate disposed on at least two sides of the channel, wherein a portion of the source is disposed in contact with a portion of the channel.