Fin-Type Active Area Semiconductor Liner Protrusion
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving both fast operating speed and high operation accuracy, particularly in the structure of transistors, which limits the performance of integrated circuit devices.
Innovation Solution
The integration of a fin-type active area with a semiconductor liner having protrusion portions and an isolation layer, along with a method of manufacturing that involves forming crystalline and amorphous semiconductor layers, allows for improved transistor performance by reducing the difference in critical dimensions and increasing the channel area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the fin-type active area is down-scaled to improve operating speed and accuracy, then the device performance improves, but the critical dimension control becomes more difficult and manufacturing precision deteriorates
Solution Approach 1:
A semiconductor liner is introduced as an intermediary layer between the fin-type active area and the isolation layer. The liner includes a protrusion portion that extends beyond the fin-type active area edge, acting as a mediator to maintain consistent critical dimensions during manufacturing processes while enabling further down-scaling of the fin structure itself.
Solution Approach 2:
The semiconductor liner with its protrusion portion is formed in advance before the isolation layer is deposited. This preliminary structure ensures that when the isolation layer is formed, the critical dimension is already predetermined by the liner's protrusion, making subsequent manufacturing steps more controllable and precise.
2Productivity
If the fin-type active area is reduced in size to improve device performance, then the channel area increases, but the consumption of the fin-type active area increases
Solution Approach 1:
The semiconductor liner serves as a protective intermediary that prevents direct contact and potential damage between the fin-type active area and the isolation layer. The protrusion portion of the liner extends beyond the fin edge, creating a buffer zone that reduces consumption of the fin-type active area during processing while still allowing the channel area to be increased through proper fin design.
3Device complexity
If the isolation layer is placed closer to the fin-type active area to improve device integration, then the device complexity reduces, but the manufacturing precision required increases
Solution Approach 1:
The semiconductor liner acts as a spacer and intermediary between the fin-type active area and the isolation layer. By forming the liner first with its protrusion portion, the isolation layer can be deposited conformally on the liner, automatically maintaining the correct spacing and positioning. This intermediary approach simplifies the overall integration process while ensuring high manufacturing precision through self-alignment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the performance of transistors by reducing the consumption of the fin-type active area, maintaining a consistent critical dimension, and increasing the channel area, thereby improving the overall performance of the integrated circuit devices.
Implementation Method 1
forming an extended crystalline semiconductor layer on a side wall of the mask pattern by crystalizing a first portion of the amorphous semiconductor layer
Data Source
AI summary
Integrated circuit devices may include a fin-type active area, a semiconductor liner contacting a side wall of the fin-type active area and including a protrusion portion protruding outward from the fin-type active area in the vicinity of an edge of an upper surface of the fin-type active area, and an isolation layer spaced apart from the fin-type active area with the semiconductor liner therebetween. To manufacture the integrated circuit devices, a crystalline semiconductor layer covering the fin-type active area with a first thickness and an amorphous semiconductor layer covering the mask pattern with a second thickness may be formed, an extended crystalline semiconductor layer covering the mask pattern may be formed by crystalizing the amorphous semiconductor layer, and a semiconductor liner including a protrusion portion may be formed from the extended crystalline semiconductor layer and the crystalline semiconductor layer.