Fin-Type Active Region Depth Variation for IC Device Optimization
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Solution Overview
Problem
As IC devices are downscaled, ensuring differently required electrical properties across various device structures on the same substrate becomes challenging, particularly due to reduced device area, which affects the optimization of transistor structures and performance.
Innovation Solution
The IC device incorporates a substrate with distinct fin-type active regions of varying depths and widths in different regions, allowing for the formation of source/drain regions and gate lines that intersect these regions, enabling efficient electrical property optimization through epitaxial growth and spacer formation, thereby enhancing transistor performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If IC devices are downscaled to reduce device area, then device area is reduced, but it becomes difficult to ensure differently required electrical properties across various device structures
Solution Approach 1:
The patent applies local quality by forming different fin depth structures in different regions of the semiconductor device. First fins have a first depth while second fins have a second depth greater than the first depth, allowing each region to be optimized for its specific electrical requirements. This enables different electrical properties to be achieved in different areas of the device while maintaining overall downscaled dimensions.
2Speed
If fin depth is increased to improve transistor performance, then operating speed is improved, but device area increases
Solution Approach 1:
The patent employs asymmetry by creating fins with different depths in different regions. The second fins have a greater depth than the first fins, allowing asymmetric optimization where regions requiring higher operating speed can utilize deeper fins while other regions use shallower fins to minimize area. This asymmetric structure enables performance optimization without proportional area increase.
3Quantity of substance
If device area is reduced through downsaling, then integration density is increased, but manufacturing precision requirements become more difficult to meet
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor device into multiple regions with different fin depth characteristics. First fins and second fins are formed as separate segmented structures with controlled different depths. This segmentation allows independent optimization and control of fin depths in different regions, making manufacturing precision more manageable compared to uniform deep fins across the entire device.
Data Source
AI summary
An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.