Fin-Type Active Region Width Segmentation for NMOS PMOS Stress Optimization
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Solution Overview
Problem
Current semiconductor technologies face challenges in optimizing the performance of transistors, particularly in achieving independent improvements based on the conductivity type of channel regions in integrated circuit devices, as existing structures do not effectively address the need for tailored performance enhancements for NMOS and PMOS transistor regions.
Innovation Solution
The development of an integrated circuit device with fin-type active regions of different widths and conductivity types, where the first fin-type active region has a first width and the second fin-type active region has a second width, both protruding from the substrate with distinct stressor liners and gate line structures, allowing for independent stress application and performance optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single fin-type active region structure is used for both NMOS and PMOS transistors, then manufacturing process is simplified, but transistor performance cannot be independently optimized for different conductivity types
Solution Approach 1:
The substrate is divided into first and second regions with different fin-type active region structures. The first fin-type active region has a first width for NMOS transistors, while the second fin-type active region has a second width for PMOS transistors. This segmentation allows independent optimization of transistor performance for different conductivity types while maintaining a unified manufacturing process flow.
Solution Approach 2:
Different regions of the substrate are assigned different fin widths and stressor liner configurations tailored to specific transistor types. NMOS regions receive tensile stressor liners while PMOS regions receive compressive stressor liners, creating local quality variations that optimize carrier mobility for each conductivity type without requiring complete process redesign.
2Reliability
If different fin widths are used for NMOS and PMOS regions, then carrier mobility is improved through tailored stress application, but device structure complexity increases
Solution Approach 1:
The device is segmented into distinct first and second regions with different fin widths. The first fin-type active region has a first width optimized for NMOS transistors, while the second fin-type active region has a second width optimized for PMOS transistors. This segmentation enables tailored stress application to improve carrier mobility for each transistor type.
Solution Approach 2:
Each region is configured with local quality variations: NMOS regions have wider fins with tensile stressor liners to enhance electron mobility, while PMOS regions have narrower fins with compressive stressor liners to enhance hole mobility. These localized optimizations improve carrier mobility without requiring complete device redesign.
3Reliability
If stressor liners are applied to improve transistor performance, then carrier mobility increases, but manufacturing process complexity and leakage control difficulty increase
Solution Approach 1:
Stressor liners are applied with local quality variations: tensile stressor liners are deposited on NMOS fin-type active regions to enhance electron mobility, while compressive stressor liners are deposited on PMOS fin-type active regions to enhance hole mobility. This localized stress application improves transistor performance while using standard deposition processes.
Solution Approach 2:
The stress state parameter is changed locally by selecting different stressor liner materials and deposition conditions. Tensile stress is applied to NMOS regions through appropriate liner material selection, while compressive stress is applied to PMOS regions, optimizing carrier mobility for each conductivity type through parameter control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved carrier mobility and performance enhancement for both NMOS and PMOS transistors by applying tailored stresses to each type of channel region, thereby optimizing transistor performance and controlling leakage currents.
Implementation Method 1
the first device isolation layer may include a first stressor liner on the first fin-type active region that imparts a tensile stress thereon, and the second device isolation layer may include a second stressor liner on the second-fin type active region that imparts a compressive stress thereon
Data Source
AI summary
An integrated circuit (IC) device includes a first-fin-type active region, a second-fin-type active region, and an inter-region stepped portion. The first-fin-type active region protrudes from a substrate in a first region of the substrate and has a first width in a first direction. The second-fin-type active region protrudes from the substrate in a second region of the substrate and has a second width in the first direction. The second width is less than the first width. The inter-region stepped portion is formed at an interface between the first region and the second region on a bottom surface, which is a portion of the substrate between the first-fin-type active region and the second-fin-type active region.