Fin-Type Semiconductor Device With Variable Trench Depths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices with multigate transistors face challenges in adjusting the positions of fin-type patterns effectively, which affects the density and scaling of semiconductor devices, and requires improved methods to control current and suppress short channel effects.
Innovation Solution
The semiconductor device incorporates fin-type patterns with varying depths and widths of trenches, along with field insulating films, to adjust the positions and orientations of these patterns, enhancing control over current flow and reducing short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fin-type patterns are formed with uniform depth and width, then manufacturing process is simple, but positions of fin-type patterns cannot be adjusted effectively
Solution Approach 1:
The patent applies local quality by creating trenches with different depths at different locations between fin-type patterns. Specifically, a first trench has a first depth and a second trench has a second depth greater than the first depth, allowing selective adjustment of fin pattern positions based on local requirements rather than uniform treatment across the entire device.
Solution Approach 2:
The patent introduces depth variation as an additional dimension of control beyond the traditional two-dimensional planar arrangement. By varying trench depth in the vertical dimension, the invention enables precise control over fin-type pattern positions and orientations, adding a new degree of freedom to the manufacturing process.
2Reliability
If gate length is increased, then current control capability is enhanced, but device scaling is limited
Solution Approach 1:
The patent transitions from two-dimensional planar control to three-dimensional control by forming trenches at varying depths. This vertical dimension enables enhanced current control through precise manipulation of fin pattern positions and orientations, achieving better electrical performance without increasing gate length.
Solution Approach 2:
The patent changes the depth parameter of trenches to control fin-type pattern positions. By adjusting trench depth rather than gate length, the invention achieves improved current control capability while maintaining compact device dimensions suitable for scaling.
3Reliability
If uniform trenches are used between fin-type patterns, then manufacturing is easier, but short channel effects cannot be suppressed effectively
Solution Approach 1:
The patent applies local quality by forming a second trench with greater depth than the first trench in specific locations. This selective depth variation targets regions where short channel effects are most pronounced, providing effective suppression where needed while maintaining simpler structures elsewhere.
Solution Approach 2:
The patent segments the trench structure into multiple depth levels, with a first trench at a first depth and a second trench at a second depth. This segmentation allows different regions to be optimized for different functions, with deeper trenches providing enhanced short channel effect suppression in critical areas.
Data Source
AI summary
A semiconductor device is provided which includes a first fin-type pattern including a first side surface and a second side surface opposite to each other, a first trench of a first depth adjacent to the first side surface, a second trench of a second depth adjacent to the second side surface. The second depth differs from the first depth, and a first field insulating film partially fills the first trench and a second field insulating film partially fills the second trench. The first fin-type pattern has a lower portion, and an upper portion having a narrower width than the lower portion, and has a first stepped portion on a boundary between the upper portion and the lower portion. The first field insulating film includes a first lower field insulating film in contact with the lower portion, and a first upper field insulating film in contact with the upper portion.