Fin-Type Active Pattern Gate Electrode Arrangement for Antifuse Current Ratio
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Solution Overview
Problem
Semiconductor devices with antifuse elements face challenges in optimizing the ratio of On current to Off current, which affects their performance and efficiency in memory applications.
Innovation Solution
The semiconductor device incorporates a specific fin-type active pattern structure with multiple gate electrodes and epitaxial layers, where the second gate electrode is not formed on the second fin-type active pattern, and the first gate electrode is disposed between the contact and the second gate electrode, optimizing the current ratio through precise arrangement and connection of these elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional antifuse structure is used, then the device is simple to manufacture, but the On current to Off current ratio is insufficient
Solution Approach 1:
The active pattern is divided into multiple fins (first fin-type active pattern and second fin-type active pattern) with different gate electrode configurations. This segmentation allows independent control of current paths, enabling high On current through multiple parallel fins while maintaining low Off current by selective gate control, thus resolving the contradiction between current ratio and device complexity.
Solution Approach 2:
Different regions of the fin-type active patterns are given different properties: the first fin-type active pattern has both first and second gate electrodes for full control, while the second fin-type active pattern has only a first gate electrode. This local quality differentiation optimizes the current ratio by controlling which fins conduct current in different states, improving reliability without excessive complexity.
2Reliability
If multiple gate electrodes are formed on all fin-type active patterns, then current control is improved, but manufacturing complexity increases
Solution Approach 1:
The second gate electrode is extracted from the second fin-type active pattern, meaning it is formed only on the first fin-type active pattern. This selective omission simplifies the manufacturing process by reducing the number of gate electrodes that need to be formed and aligned, while still achieving good current control through the first gate electrode and the differential fin structure.
Solution Approach 2:
Instead of forming gate electrodes on all fins uniformly, the invention inverts the approach by deliberately omitting the second gate electrode from the second fin-type active pattern. This unconventional arrangement simplifies manufacturing while maintaining effective current control through the remaining gate structures and fin configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the On current to Off current ratio, improving the performance and efficiency of the antifuse memory devices by optimizing the electrical connections and insulation layers, thereby enhancing their memory storage capabilities.
Implementation Method 1
programmed by electrically short-circuiting with a breakdown mechanism when a high voltage is applied to a thin gate oxide layer
Implementation Method 2
When a sufficiently high voltage is applied to the terminals, silicon dioxide or such non-conductive material becomes a short circuit or a low-resistance conductive path between the two terminals
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes: a plurality of fin-type active patterns which extend along a first direction, and are arranged with respect to each other along a second direction different from the first direction; a contact which is electrically connected to the plurality of fin-type active patterns; a first gate electrode which extends along the second direction and is formed on at least two of the plurality of fin-type active patterns; and a second gate electrode which extends along the second direction and is formed on at least one of the plurality of fin-type active patterns. The first gate electrode is disposed between the contact and the second gate electrode, and the number of fin-type active patterns intersected by the first gate electrode is greater than the number of fin-type active patterns intersected by the second gate electrode.