Fin-Type Gate Semiconductor Cell With Varying Oxide Thickness
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Solution Overview
Problem
As semiconductor devices become more highly integrated, the critical dimension of gates decreases, leading to a short channel effect that degrades the performance of field effect transistors and makes it difficult to control the sub-threshold swing of fin-type gates in semiconductor cells with line-type active regions and isolation layers.
Innovation Solution
A semiconductor cell design that includes a line-type device isolation layer, first and second trenches forming fin-type active regions, and oxide layers with varying thicknesses to improve the sub-threshold swing and gate performance, with a gate conductive layer and insulating layer formed over these structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the critical dimension of the gate is reduced to increase integration density, then the number of devices per chip area increases, but the short channel effect degrades the performance of field effect transistors
Solution Approach 1:
The patent transitions from planar gates to three-dimensional fin-type gates, extending the active region vertically from the substrate surface. This dimensional change increases the effective channel width without increasing the planar footprint, thereby maintaining integration density while improving gate control and reducing short channel effects through enhanced electrostatic control.
Solution Approach 2:
The patent divides the gate structure into multiple segments: the buried gate formed in the trench at the base of the fin, and the overlying gate electrode. This segmentation allows independent optimization of each gate component, enabling precise control of threshold voltage and electrostatic characteristics to mitigate short channel effects while maintaining high integration density.
2Reliability
If the fin type gate is used to improve gate performance and sub-threshold swing, then the contact area between active region and gate increases, but it becomes difficult to control the gate surrounding the fin shaped substrate as critical dimension decreases
Solution Approach 1:
The gate structure is segmented into a buried gate portion formed in the trench and an overlying gate electrode. This segmentation simplifies the control mechanism by separating the electrostatic control function (buried gate) from the channel formation function (fin structure), making it easier to manage gate characteristics even as critical dimensions decrease.
Solution Approach 2:
The patent introduces an intermediary layer structure between the fin-type active region and the gate electrode, including dielectric layers and doping regions. This intermediary structure acts as a mediator to enhance gate control by providing electrical isolation and controlling the electric field distribution, thereby improving sub-threshold swing while managing the complexity of controlling gates around fin structures.
Data Source
AI summary
A semiconductor cell includes first trenches defining fin type active regions within the semiconductor substrate and adjacent to each other, second trenches disposed at one side and the other side of the first trenches, adjacent to the first trench and including fin type active regions, a first oxide layer formed on each of surfaces of the first trenches, and a second oxide layer formed on each of surfaces of the second trenches and having a thicker thickness than the first oxide layer. Although the critical dimension of the fin is increased, the gate drivability can be improved.