Fin-Type Nonvolatile Memory Coupling Ratio
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Solution Overview
Problem
The flat cell structure in nonvolatile semiconductor memory devices faces challenges in achieving a sufficient coupling ratio due to the small area where floating gate electrodes and control gate electrodes face each other, leading to inter-cell interference when trying to miniaturize further.
Innovation Solution
A fin-type active area with a taper shape is used, featuring a charge storage layer and a control gate electrode that extends in the direction perpendicular to the row direction, with an inter-electrode insulating layer of high dielectric constant to improve coupling ratio while preventing inter-cell interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a flat cell structure is used to enable miniaturization, then the half pitch of bit lines can be reduced, but the coupling ratio between floating gate electrodes and control gate electrodes becomes insufficient
Solution Approach 1:
The patent transitions from a planar flat cell structure to a three-dimensional Fin-type structure. The active area is formed as a vertical fin extending from the semiconductor substrate, allowing the control gate electrode to wrap around the fin structure. This dimensional change increases the overlapping area between the control gate and floating gate electrodes without increasing the planar footprint, thereby improving coupling ratio while maintaining miniaturization.
Solution Approach 2:
The control gate electrode is designed to wrap around the Fin-type active area, with the inter-electrode insulating layer positioned between them. This nested configuration allows the control gate to surround the floating gate structure in multiple directions, increasing the effective coupling area. The insulating layer is strategically placed within this nested structure to provide electrical isolation while maintaining close proximity for strong coupling.
2Length of moving object
If the half pitch is narrowed to improve miniaturization, then device density increases, but inter-cell interference occurs between memory cells in the row direction
Solution Approach 1:
The patent introduces an inter-electrode insulating layer as an intermediary substance positioned between the control gate electrode and the floating gate electrode. This insulating layer with high dielectric constant provides electrical isolation that prevents charge leakage and interference between adjacent memory cells in the row direction, while still allowing strong capacitive coupling through its high-k property. This mediator enables narrow pitch without inter-cell interference.
3Reliability
If the area where floating gate electrodes and control gate electrodes face each other is increased to improve coupling ratio, then device area increases, but miniaturization is compromised
Solution Approach 1:
The patent utilizes vertical dimension by forming Fin-type active areas that extend upward from the substrate. The control gate electrode wraps around these vertical fins, creating overlapping areas in the vertical direction rather than only in the planar direction. This allows increased coupling area without increasing the planar device footprint, enabling both high coupling ratio and miniaturization.
Solution Approach 2:
The patent employs a composite structure combining the Fin-type active area (semiconductor material), inter-electrode insulating layer (high-k dielectric material), control gate electrode (conductive material), and floating gate electrode (conductive material). This composite structure maximizes the effective coupling area through the vertical fin and wrapped gate configuration while maintaining compact planar dimensions, achieving high coupling ratio without compromising miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the coupling ratio of memory cells, allows for miniaturization without inter-cell interference, and provides adjustable coupling ratios for optimal performance.
Implementation Method 1
a second insulating layer covering the upper surface of the charge storage layer; and a control gate electrode on the second insulating layer
Data Source
AI summary
According to one embodiment, a device includes a fin type active area on a semiconductor substrate, the active area having an upper surface with a taper shape, having a width in a first direction, and extending in a second direction intersect with the first direction, a first insulating layer on the active area, a charge storage layer on the first insulating layer, the charge storage layer having an upper surface with a taper shape, a second insulating layer covering the upper surface of the charge storage layer, and a control gate electrode on the second insulating layer, the control gate electrode extending in the first direction.