Fin-Type Memory Cells With Sub-Lithographic Spacers
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Solution Overview
Problem
Conventional resistive-type non-volatile memories, such as PCRAMs and RRAMs, face inefficiencies due to large memory elements leading to high power consumption and resistance state margin issues.
Innovation Solution
The development of fin-type memory cells with small memory elements, where fin stacks with sub-lithographic dimensions are formed on a substrate, reducing the heater-to-memory element contact area and limiting conductive filament current paths, thereby improving heating efficiency and resistance distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional large memory elements are used, then manufacturing is easier, but power consumption increases and heating efficiency decreases
Solution Approach 1:
The patent transitions from planar 2D memory elements to three-dimensional fin-stack structures. The fin stacks extend vertically from the substrate, creating a 3D configuration that reduces the lateral footprint while maintaining or increasing functional volume. This dimensional change enables smaller effective memory element areas with improved heating efficiency and reduced power consumption.
Solution Approach 2:
The memory element is divided into multiple fins within a stack configuration. Instead of a single large planar element, the functionality is segmented across multiple vertical fins, each contributing to the overall memory function. This segmentation allows for reduced individual fin dimensions while collectively achieving the required performance, thereby reducing power consumption and improving heating efficiency.
2Reliability
If conventional large memory elements are used, then device fabrication is simpler, but resistance state margins deteriorate
Solution Approach 1:
By moving to 3D fin-stack structures, the patent achieves better control over resistance states through the vertical dimension. The fin stacks provide more uniform current distribution and better-defined switching regions, improving resistance state margins while maintaining manufacturability through standard lithographic processes combined with self-aligned fabrication techniques.
3Area of moving object
If sub-lithographic fin stacks are formed, then memory element size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary patterning steps where mandrels and spacers are formed before the final fin-stack definition. This preliminary action establishes a framework that guides subsequent self-aligned etching processes, enabling sub-lithographic feature sizes to be achieved without requiring direct lithographic patterning of the final fin dimensions. The multi-step preliminary fabrication approach reduces the memory element area while managing complexity through systematic process design.
4Power
If fin stacks with reduced contact area are used, then heating efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The vertical fin-stack configuration concentrates the heating function in the vertical dimension rather than spreading it laterally. This dimensional redistribution reduces the lateral contact area between heating elements and memory material, improving heating efficiency. The vertical extent of the fins compensates for the reduced lateral footprint, maintaining sufficient interaction volume while achieving the desired compact footprint and improved thermal performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced power consumption and enhanced resistance state margins, enabling more efficient data storage and improved performance in resistive-type memories.
Implementation Method 1
the memory element switches between the amorphous and crystalline phases. Switching between the two phases is achieved by heating the memory element using a heater
Implementation Method 2
the memory element switches between the insulating and conducting phases by creating or destroying conductive filaments
Data Source
AI summary
Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells.