Fin-Type Semiconductor Device Asymmetric Source-Drain Current Control
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Solution Overview
Problem
Current semiconductor devices face challenges in effectively scaling and controlling current without increasing gate length, particularly in suppressing short channel effects in multigate transistors.
Innovation Solution
The semiconductor device design incorporates fin-type patterns with specific cross-sectional shapes and gate electrode configurations, including convex polygonal and irregular shapes, to enhance current control and reduce short channel effects, with source/drain regions spaced differently on each side of the gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate length is increased to control current, then current control capability is improved, but device scaling is hindered
Solution Approach 1:
The patent transitions from planar gate control to three-dimensional fin-type channel structure, where the channel extends vertically from the substrate. This dimensional change allows the gate to control current through the fin height rather than requiring increased gate length, achieving better current control while maintaining scaled-down lateral dimensions.
Solution Approach 2:
The channel region is segmented into multiple fin-type patterns protruding from the substrate, creating a multigate structure. This segmentation allows the gate to control current through multiple fin surfaces simultaneously, enhancing current control capability without increasing the overall gate length.
2Ease of manufacture
If conventional planar transistor structure is used, then manufacturing is simple, but short channel effects cannot be effectively suppressed
Solution Approach 1:
The patent introduces vertical fin structures protruding from the substrate, transforming the conventional planar channel into a three-dimensional multigate configuration. This dimensional change provides superior electrostatic control over the channel, effectively suppressing short channel effects while maintaining compatibility with standard semiconductor manufacturing processes.
3Ease of manufacture
If source/drain regions are uniformly spaced on both sides of gate electrode, then manufacturing is simplified, but current control is suboptimal
Solution Approach 1:
The patent employs asymmetric source/drain spacing relative to the gate electrode, with different spacing distances on opposite sides. This asymmetric configuration optimizes current control by creating non-uniform electric field distribution, improving device performance while remaining manufacturable through standard lithography and deposition processes.
Data Source
AI summary
A semiconductor device includes a substrate having first and second regions, a first fin-type pattern and a second fin-type pattern formed in the first region and extending in a first direction, and a third fin-type pattern and a fourth fin-type pattern formed in the second region and extending in a third direction. A first source/drain is formed on the first fin-type pattern and a second source/drain region is formed on the second fin-type pattern. Each of first and second source/drains have a cross section defining a same convex polygonal shape. A third source/drain is formed on the third fin-type pattern and a fourth source/drain region is formed on the fourth fin-type pattern. Cross-sections of the third and fourth source/drains define different convex polygonal shapes from one another.