Fin-Type Semiconductor Layer Crystal Orientation Control
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Solution Overview
Problem
The vapor phase epitaxy method used in fin FETs often results in non-homogeneous semiconductor layer growth due to the formation of facets with undesired crystal orientations on the side faces of raised semiconductor layers, leading to issues with silicide formation and increased parasitic resistance.
Innovation Solution
A semiconductor device and manufacturing method that form a fin-type semiconductor layer with a {110} crystal plane on its side faces, using a combination of masking, ion implantation, and solid phase epitaxy to create a convex-shaped semiconductor layer with controlled crystal orientation, allowing for parallel and advanced crystal planes in source and drain regions compared to the channel region, thereby preventing facet formation and reducing parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the vapor phase epitaxy method is used to form a raised semiconductor layer, then the semiconductor layer can be grown, but the crystal plane having a desired crystal orientation cannot be formed on side faces and a facet with undesired crystal orientation is formed instead
Solution Approach 1:
The patent changes the fundamental growth method from vapor phase epitaxy to solid phase epitaxy. This parameter change in the growth process enables the formation of crystal planes with desired crystal orientation on the side faces of the raised semiconductor layer, preventing facet formation with undesired orientation while ensuring homogeneous growth throughout the layer.
2Length of moving object
If a raised semiconductor layer is formed to ensure silicide formation region, then elements can be made finer, but parasitic resistance increases due to facet formation
Solution Approach 1:
By changing from vapor phase epitaxy to solid phase epitaxy, the patent eliminates facet formation on the side faces of the raised semiconductor layer. This enables the raised layer to be formed with proper crystal orientation, allowing silicide to be successfully formed on the side faces and reducing parasitic resistance while maintaining fine element dimensions.
3Ease of manufacture
If vapor phase epitaxy is used for raising the semiconductor layer surface, then the layer can be formed, but non-homogeneous growth occurs leading to poor silicide formation
Solution Approach 1:
The patent changes the growth method parameter from vapor phase epitaxy to solid phase epitaxy. This enables homogeneous growth of the raised semiconductor layer with uniform crystal structure throughout, ensuring that silicide can be properly formed on all surfaces including side faces, while maintaining ease of manufacture through a controlled solid phase transformation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a raised semiconductor layer with improved crystal orientation, reducing parasitic resistance and enhancing transistor characteristics by ensuring uniform crystal growth and effective silicide formation.
Implementation Method 1
selectively forming the amorphous semiconductor film formed on the top face and side faces into single crystals and thereby forming a raised semiconductor layer
Implementation Method 2
performing ion implantation of predetermined impurities into the picked-up semiconductor layer by using the gate electrode and the side wall insulation film as a mask, and thereby forming a source region and a drain region
Data Source
AI summary
This disclosure concerns a semiconductor device comprising a convex-shaped semiconductor layer formed on a semiconductor substrate; an insulation film formed on the semiconductor substrate, the insulation film having a film thickness to the extent that a lower part of the semiconductor layer is buried; a gate electrode formed on a set of both opposed side faces via a gate insulation film; and a source region and a drain region formed on a side face side on which the gate electrode is not formed in the semiconductor layer, wherein the semiconductor layer is formed so as to dispose surfaces of a peripheral part excepting a central part on an outer side than surfaces of the central part covered by at least the gate electrode.