Fin-Type Semiconductor Device Fabrication via Mandrel-Spacer Patterning
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Solution Overview
Problem
Current semiconductor device fabrication techniques face challenges in achieving improved operating characteristics, particularly in scaling multi-gate transistors with three-dimensional channels, which affect current control and short channel effects.
Innovation Solution
A method involving sequential formation of hard mask layers, sacrificial layers, and spacers to create fin-type patterns and gate electrodes, with specific spacing and patterning techniques to form active fins and gate electrodes without step differences, allowing for improved transistor design and reduced short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate transistors with three-dimensional channels are used, then current controlling capability is improved and short channel effects are suppressed, but device fabrication complexity increases
Solution Approach 1:
The fabrication process is divided into multiple sequential stages: forming first and second mandrels with different pitches, selectively removing alternate mandrels, forming spacers on remaining mandrels, and iterative etching to create the multi-gate structure. This segmentation transforms a complex single-step process into manageable sequential operations, enabling precise control of the three-dimensional channel geometry while maintaining fabrication feasibility
Solution Approach 2:
The patent transitions from two-dimensional planar transistor fabrication to three-dimensional multi-gate structures by forming vertical fins and wrapping gates around them. The mandrel-spacer methodology enables creation of these 3D structures through controlled lateral and vertical deposition, achieving superior current control and short channel effect suppression through the added dimensional complexity
2Productivity
If fin-type patterns are densely spaced to increase device density, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The spacer formation process is self-aligned, where the spacer width is determined by the deposition thickness rather than requiring precise lithographic patterning. This self-service mechanism automatically ensures uniform spacing between fins, achieving high manufacturing precision even at dense pitch configurations without requiring ultra-precise alignment steps
Solution Approach 2:
Mandrels are formed in advance with relaxed pitch requirements, and the final fine-pitch fin structure is created through spacer deposition and selective mandrel removal. This preliminary action allows the critical dimension to be defined by controllable deposition processes rather than difficult lithography, enabling dense spacing with maintained manufacturing precision
Data Source
AI summary
A method of forming a semiconductor device includes sequentially forming a hard mask layer and a first sacrificial layer on a substrate, forming a first mandrel on the first sacrificial layer, forming a first spacer on both sidewalls of the first mandrel, removing the first mandrel, forming a second mandrel by etching the first sacrificial layer using the first spacer as an etch mask, forming a second spacer on both sidewalls of the second mandrel, removing the second mandrel, forming a hard mask pattern by patterning the hard mask layer using the second spacer as an etch mask, the hard mask pattern including first to ninth fin-type mask patterns extending to be parallel with each other in a first direction and sequentially spaced apart from each other in a second direction perpendicular to the first direction, removing the third, fifth and seventh fin-type mask patterns, forming first to sixth active patterns by etching the substrate using the hard mask pattern as an etch mask, and forming a first gate electrode extending in the second direction to intersect the first to fourth active patterns and a second gate electrode extending in the second direction to intersect the third to sixth active patterns and spaced apart from the first gate electrode in the first direction without intersecting the first and second active patterns.