FIN-Type Semiconductor Memory Device With Variable Thickness Floating Body
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Solution Overview
Problem
The existing FBC memory devices face challenges in achieving a small BOX layer thickness and high signal difference between data '0' and '1' due to technical difficulties in reducing the BOX layer to 50 nm or below, which results in high contact resistance in source/drain regions requiring lengthy or high-temperature annealing processes.
Innovation Solution
A FIN-type semiconductor memory device is developed with a FIN-type semiconductor layer having a floating body region and source/drain regions of different thicknesses, where the floating body region is thinner than the source/drain regions, allowing for full depletion and reduced contact resistance through oblique ion implantation and shorter, lower-temperature annealing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the FIN-type semiconductor layer thickness is reduced to increase signal difference between data '0' and data '1', then the floating body region achieves full depletion and signal amount increases, but the source/drain regions also have reduced thickness leading to high contact resistance
Solution Approach 1:
The patent applies local quality by creating different thickness regions within the same FIN-type semiconductor layer. The floating body region has a first thickness (50 nm or less) to achieve full depletion and high signal difference, while the source/drain regions have a second thickness (greater than the first thickness) to maintain low contact resistance. This local differentiation allows each region to be optimized for its specific function without compromising the other.
2Reliability
If conventional annealing processes are used to diffuse impurity in source/drain regions with small thickness, then impurity diffusion occurs, but the channel region is also affected changing memory cell characteristics
Solution Approach 1:
The patent uses local quality to protect different regions during annealing. The source/drain regions have increased thickness providing a buffer zone that allows impurity diffusion without significantly affecting the channel region. The gate insulation films on the side surfaces of the floating body region provide localized protection, confining the annealing effect to the source/drain regions while preserving channel characteristics.
Solution Approach 2:
The patent applies preliminary action by forming the gate insulation films on the side surfaces of the floating body region before the annealing process. These gate insulation films act as protective barriers that prevent impurity diffusion into the channel region during the subsequent annealing process, allowing the source/drain regions to be properly doped without compromising the channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the signal difference between data '0' and '1' while maintaining low contact resistance, allowing for efficient data storage without the need for prolonged or high-temperature annealing, thus improving the performance of the memory device.
Implementation Method 1
A back bias is applied to the FBC memory device from the back gate electrode, thereby the floating body region is fully depleted
Implementation Method 2
Impurity is usually implanted into the source/drain regions from above the FIN toward the upper surface of the FIN
Implementation Method 3
In order to diffuse impurity in the total source/drain regions, annealing process is necessary for a long time or at a high temperature
Data Source
AI summary
This discloser concerns a semiconductor device including an insulation layer; a FIN-type semiconductor layer provided on the insulation layer and including a floating body region in an electrically floating state and including a source region and a drain region at both sides of the floating body region; gate insulation films provided on both side surfaces of the floating body region; gate electrodes provided on both side surfaces of the floating body region via the gate insulation films; and a source electrode and a drain electrode respectively contacting with the upper surface of the source region and the drain region, wherein in the cross section of the FIN-type semiconductor layer in parallel with the surface of the insulation layer, a thickness of the FIN-type semiconductor layer in the floating body region is smaller than a thickness of the FIN-type semiconductor layer in the source and the drain regions.