Fin-Type Semiconductor Device With Shallow Trench Gate Control
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing operating performance and reliability, particularly in the scaling of multi-gate transistors where the integration density and suppression of short channel effects are limited by existing fin-shape silicon body configurations.
Innovation Solution
A semiconductor device design featuring a shallow trench at the border between a tapered fin-type pattern and an active region, with a field insulating film surrounding the fin-type patterns, and a gate electrode intersecting these patterns, allowing for improved current control and reduced short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-gate transistor with fin-shape silicon body is used for scaling, then integration density is improved, but short channel effects are not sufficiently suppressed
Solution Approach 1:
The device is divided into multiple fins (first fin-type pattern, second fin-type pattern, third fin-type pattern) arranged in parallel, with each fin acting as an independent channel. This segmentation allows for better control of the channel region and suppression of short channel effects while maintaining high integration density through the multi-fin configuration.
Solution Approach 2:
The invention transitions from a planar channel structure to a three-dimensional multi-fin structure extending in the vertical dimension. The fins are arranged parallel to each other and extend in the third direction, creating a multi-dimensional channel architecture that enhances gate control and suppresses short channel effects while improving integration density.
2Reliability
If the gate length is increased to suppress short channel effects, then reliability is improved, but current control capability deteriorates
Solution Approach 1:
The gate electrode is positioned to overlap with specific end portions of the fin-type patterns, creating localized control regions. The first gate electrode overlaps with the end portion of the first fin-type pattern, and the second gate electrode overlaps with the end portion of the second fin-type pattern, allowing for optimized local control of current flow while maintaining overall device performance.
Solution Approach 2:
The gate electrodes are positioned in advance to overlap with the end portions of the fin-type patterns before the actual operation. This preliminary positioning of the gate electrodes over the end portions of the fins enables pre-established control over the channel region, ensuring effective current control and short channel effect suppression from the outset.
3Reliability
If tapered fin-type patterns are used, then operating performance is improved, but manufacturing complexity increases
Solution Approach 1:
The fin-type patterns are designed with asymmetric geometries, including tapered configurations where the width varies along the length of the fins. The first fin-type pattern, second fin-type pattern, and third fin-type pattern each have specific asymmetric shapes that optimize operating performance by controlling current distribution and electric field characteristics, while the asymmetry is managed through systematic fabrication approaches.
Data Source
AI summary
A semiconductor device comprises a first fin-type pattern comprising a first long side extending in a first direction, and a first short side extending in a second direction. A second fin-type pattern is arranged substantially parallel to the first fin-type pattern. A first gate electrode intersects the first fin-type pattern and the second fin-type pattern. The second fin-type pattern comprises a protrusion portion that protrudes beyond the first short side of the first fin-type pattern. The first gate electrode overlaps with an end portion of the first fin-type pattern that comprises the first short side of the first fin-type pattern. At least part of a first sidewall of the first fin-type pattern that defines the first short side of the first fin-type pattern is defined by a first trench having a first depth. The first trench directly adjoins a second trench having a second, greater, depth.