Fin-Type IC Work Function Control Layer Step Portion

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Solution Overview

Problem

The increasing demand for high integration and downscaling of integrated circuit devices leads to a short channel effect in transistors, reducing the reliability of these devices, which existing technologies have struggled to address effectively.

Innovation Solution

An integrated circuit device with a multi-gate structure is proposed, featuring fin-type active areas, element isolation layers, and specific gate structures with work function control layers to optimize the threshold voltage control and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If integrated circuit devices are downscaled to achieve high integration, then device density and integration level are improved, but short channel effect increases and reliability deteriorates

Engineering Contradiction:
Improveintegration levelVSAvoiddevice reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The gate structure is segmented into multiple gates (first gate structure and second gate structure) positioned at different locations (front gate and back gate) to independently control different portions of the channel. This segmentation allows separate control of threshold voltage and carrier flow, enabling effective suppression of short channel effect while maintaining high integration density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from planar 2D channel control to 3D multi-gate control by adding a back gate structure beneath the channel region. This dimensional extension provides an additional control dimension for managing channel characteristics, effectively counteracting short channel effects in scaled devices

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If work function control layer thickness is increased to control threshold voltage, then threshold voltage control precision is improved, but device performance and efficiency deteriorate

Engineering Contradiction:
Improvethreshold voltage control precisionVSAvoiddevice performance
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The work function control layer is applied selectively with different thicknesses in different regions: a first thickness in the first active area and a second thickness in the second active area. This local differentiation enables precise threshold voltage control for each transistor type (n-type and p-type) while optimizing overall device performance through region-specific tuning

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention controls threshold voltage by adjusting the thickness parameter of the work function control layer rather than changing material composition. By varying thickness locally across different active areas, precise threshold voltage control is achieved while maintaining optimal device performance characteristics

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11031392B2Integrated circuit device having a work function control layer with a step portion located on an element isolation layer
Publication Date: 2021.06.08 SAMSUNG ELECTRONICS CO LTD
  • US11031392B2 patent drawing
  • US11031392B2 patent drawing
  • US11031392B2 patent drawing

AI summary

An integrated circuit device includes a first fin-type active area and a second fin-type active area protruding from a substrate and extending in a first direction, an element isolation layer between the first and second fin-type active areas on the substrate, first semiconductor patterns being on a top surface of the first fin-type active area and having channel areas, second semiconductor patterns being on a top surface of the second fin-type active area and having channel areas, a first gate structure extending on the first fin-type active area in a second direction and including a first work function control layer surrounding the first semiconductor patterns and comprising a step portion on the element isolation layer, and a second gate structure extending on the second fin-type active area in the second direction and including a second work function control layer surrounding the second semiconductor patterns.