Fin-shaped structure wavy profile mitigation
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Solution Overview
Problem
The formation of multi-gate devices, such as MBC transistors, is hindered by wavy sidewall profiles resulting from differential etch rates of semiconductor layers, leading to incomplete removal of dummy gate stacks and potential damage to source/drain features during the fabrication process.
Innovation Solution
The method involves epitaxially depositing a silicon liner on the fin-shaped structure to compensate for the wavy sidewall profile, followed by the deposition of a second silicon liner, which facilitates the complete removal of sacrificial layers and reduces the risk of damaging source/drain features by smoothing out the sidewall profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an anisotropic etch process is used to form fin-shaped structures with alternating semiconductor layers, then the multi-gate device structure is formed, but wavy sidewall profiles occur due to different etch rates of different semiconductor layers
Solution Approach 1:
A dummy gate stack is formed over the fin-shaped structure before the actual gate structure is created. This preliminary dummy gate serves as a placeholder that protects the fin structure during subsequent processing steps, particularly during source/drain feature formation, preventing direct damage to the wavy sidewalls while allowing the structure to be completed
Solution Approach 2:
The dummy gate stack acts as an intermediary element between the fin-shaped structure and the final gate structure. It mediates the processing by providing a protective layer that can be temporarily removed and replaced, allowing the wavy sidewall issue to be managed without compromising the overall device fabrication
2Productivity
If the dummy gate stack is removed from the wavy fin-shaped structure, then the actual gate structure can be formed, but incomplete removal occurs and source/drain features may be damaged
Solution Approach 1:
The dummy gate stack is formed in advance as a removable placeholder. This preliminary structure allows subsequent source/drain features to be formed without directly exposing and potentially damaging the wavy fin sidewalls. The dummy gate can be completely removed later without risking source/drain damage because it serves as a protective sacrificial layer during critical processing steps
Solution Approach 2:
The dummy gate stack provides beforehand cushioning protection to the fin-shaped structure during source/drain feature formation. It cushions against potential damage to the wavy sidewalls by absorbing mechanical stress and preventing direct contact between processing tools and the vulnerable fin structures, ensuring complete and safe removal later
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures the accurate removal of sacrificial layers and minimizes damage to source/drain features, enhancing the yield and reliability of the semiconductor device fabrication process.
Implementation Method 1
epitaxially depositing a first silicon liner over the fin-shaped structure
Data Source
AI summary
Methods of rectifying a sidewall profile of a fin-shaped stack structure are provided. An example method includes forming, on a substrate, a first fin-shaped structure and a second fin-shaped structure each including a plurality of channel layers interleaved by a plurality of sacrificial layers; depositing a first silicon liner over the first fin-shaped structure and the second fin-shaped structure; depositing a dielectric layer over the substrate, the first fin-shaped structure and the second fin-shaped structure; etching back the dielectric layer to form an isolation feature between the first fin-shaped structure and the second fin-shaped structure and to remove the first silicon liner over the first fin-shaped structure and the second fin-shaped structure to expose sidewalls of the plurality of channel layers and the plurality of sacrificial layers, and epitaxially depositing a second silicon liner over the exposed sidewalls of the plurality of channel layers and the plurality of sacrificial layers.