Fin Width Control in Semiconductor Fabrication via Dielectric Compensation
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Solution Overview
Problem
In semiconductor fabrication, the reduction in size of field effect transistors (FETs) leads to issues with polysilicon gate adaptation, and the 3D fin FET structure faces challenges due to uneven fin width reduction during the oxide layer formation and annealing process, affecting device performance.
Innovation Solution
A method is developed to maintain the width of isolated fins by forming a first dielectric layer over mandrels, which compensates for silicon consumption during annealing, ensuring the fin width remains comparable to densely loaded areas through controlled dielectric layer thickness and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FCVD with annealing is used to form oxide layer over fins, then oxide quality is improved, but isolated fin width is significantly reduced
Solution Approach 1:
The patent applies different dielectric layer configurations to different fin regions. Isolated fins receive a first dielectric layer with thickness in the range of 1-5 nm (compensating for oxidation), while densely loaded fins have this layer removed. This local differentiation allows isolated fins to maintain width during annealing while preserving oxide quality for all fins.
Solution Approach 2:
The first dielectric layer is formed on isolated fins before the oxide deposition and annealing process. This preliminary protective layer compensates for the silicon consumption that occurs during annealing, ensuring that isolated fins maintain their width despite the high-temperature processing required for quality oxide formation.
2Productivity
If fin size is reduced to increase device density, then device loading is improved, but isolated fin performance deteriorates
Solution Approach 1:
The patent selectively applies the first dielectric layer only to isolated fins based on their spatial distribution and loading conditions. This allows densely loaded fins to maintain their reduced size for high device density, while isolated fins receive additional width compensation to maintain performance, thus resolving the contradiction between device density and isolated fin performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents significant reduction in fin width for isolated fins, maintaining performance consistency with densely loaded fins, thereby addressing the issue of uneven fin width reduction and enhancing device reliability.
Implementation Method 1
An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins
Implementation Method 2
depositing oxide over the substrate to form an oxide layer covering the fins
Implementation Method 3
perform annealing over the substrate
Data Source
AI summary
A method for fabricating a semiconductor structure includes forming a plurality of mandrels over a substrate, wherein the substrate comprises a semiconductor substrate as a base. Then, a first dielectric layer is formed to cover on a predetermined mandrel of the mandrels. A second dielectric layer is formed over the substrate to cover the mandrels. The mandrels are removed, wherein a remaining portion of the first dielectric layer and the second dielectric layer at a sidewall of the mandrels remains on the substrate. An anisotropic etching process is performed over the substrate until a top portion of the semiconductor substrate is etched to form a plurality of fins corresponding to the remaining portion of the first dielectric layer and the second dielectric layer.