FinFET Fin Width Trimming via Dummy Gate Support
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices shrink, conventional planar MOS transistors face weakened control over channel current and increased short channel effects, necessitating improved gate-to-channel control, particularly in FinFETs with different fin widths to enhance performance.
Innovation Solution
A method involving forming initial fin structures on a semiconductor substrate, creating a dummy gate structure, and performing trimming processes to reduce the width of these fins, while maintaining the integrity of the structure to prevent deformation and cracking, thereby forming fin structures with desired dimensions for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of fin structures is reduced to improve gate-to-channel control and suppress short channel effects, then device performance is improved, but the fins become more susceptible to deformation and cracking during fabrication
Solution Approach 1:
The method performs preliminary actions by forming a dummy gate structure before trimming the fins. This dummy gate provides structural support during the trimming process, preventing fin deformation and cracking. The dummy gate is formed to extend across the fins, creating a protective framework that maintains fin integrity while width reduction is performed.
Solution Approach 2:
The dummy gate structure serves as a cushioning element that absorbs mechanical stress during the trimming process. By having this protective structure in place before trimming begins, the fins are shielded from forces that would cause deformation or cracking. The dummy gate acts as a buffer that protects the vulnerable narrow fins during fabrication.
2Ease of manufacture
If conventional planar MOS transistor structures are used to maintain simple fabrication, then manufacturing ease is maintained, but control capability over channel current is weakened and short channel effects increase
Solution Approach 1:
The invention applies local quality by creating fins with different widths at different locations. The trimming process selectively removes material from specific regions to create varied fin widths across the device. This local differentiation allows different portions of the device to have optimized characteristics for their specific functions while maintaining overall fabrication simplicity.
Solution Approach 2:
The fin structure is segmented into multiple regions with different widths through the trimming process. Instead of a uniform fin structure, the device has segments with varying dimensions that can be independently optimized. This segmentation allows the device to achieve complex performance characteristics while using a relatively simple fabrication approach.
3Reliability
If fins with two different critical dimensions are formed to suppress DIBL effect, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The dummy gate structure is formed as a preliminary action that simplifies subsequent trimming operations. By having the dummy gate in place before trimming, the process of creating fins with different critical dimensions becomes more straightforward. The dummy gate serves as a template and protective element that guides the trimming process, reducing overall fabrication complexity.
Data Source
AI summary
Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region; forming a plurality of first initial fin structures on the first region of the semiconductor substrate; forming a dummy gate structure across the first initial fin structures by covering portions of top and sidewall surfaces of the first initial fin structures; forming a dielectric layer covering sidewall surfaces of the dummy gate structure and exposing a top surface of the dummy gate structure; removing the dummy gate structure to form a first opening in the dielectric layer and expose portions of top and sidewall surfaces of the first initial fin structures; and performing at least one trimming process on the first initial fin structures to form fin first structures. A width of each first fin structure is smaller than a width of each first initial fin structure.