Find-First-Set Bit Circuit With Hierarchical Delay Reduction
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Solution Overview
Problem
Current find-first-set logic circuits introduce significant delay as the number of bits in the input data word increases, exceeding acceptable limits in large entry counts.
Innovation Solution
The method generates n n-bit patterns for an n-bit input word, where each pattern corresponds to a bit position, and combines them into a merged pattern to identify the rightmost bit with a logic 1 value efficiently, using a translator circuit, merge circuit, and indicator circuit to produce an output pattern with a logic 1 value in one position and logic 0 in others.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current find-first-set logic circuits are used, then the first set bit can be identified, but significant delay is introduced as the number of bits increases
Solution Approach 1:
The patent divides the n-bit input word into multiple groups of bits (e.g., 4-bit groups). Each group is processed by a separate find-first-set circuit, allowing parallel operation. The groups are then processed hierarchically, with carry signals propagating between groups to identify the overall first set bit. This segmentation reduces the critical path delay from O(n) to O(log n) by breaking down the single long logic path into multiple shorter parallel paths.
2Adaptability or versatility
If the number of bits in the input data word increases, then more entries can be managed, but the delay introduced in finding the first set bit exceeds acceptable limits
Solution Approach 1:
The patent transitions from a one-dimensional linear search approach to a two-dimensional hierarchical approach. The first dimension processes bits within each group in parallel, while the second dimension processes the groups themselves in a tree-like hierarchy. This dimensional change allows the circuit to scale to larger input sizes without proportionally increasing delay, as the critical path grows logarithmically rather than linearly with the number of bits.
Data Source
AI summary
Finding the first bit that is set in an n-bit input word includes generating n n-bit patterns from an n-bit input word. If the bit at one bit position of the input word has a logic 1 value, a corresponding pattern has a logic 1 value in a corresponding bit position and in each bit position left of the corresponding bit position, and a logic 0 value in each bit position right of the corresponding bit position. If the bit at the one bit position of the input word has a logic 0 value, the corresponding pattern has a logic 0 value in every bit position. The n patterns are combined into one merged n-bit pattern. An output n-bit pattern is generated from the merged n-bit pattern. The output pattern has a logic 1 value in one bit position that is the same as the rightmost bit position of the input word having a logic 1 value, and a logic 0 value in every other bit position.