Fine-Grain Clock Gating Using Data Comparison in Flip-Flops
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In integrated circuits, there is a trade-off between reducing power consumption and data setup time, particularly when using dynamic flip-flops, which can be limited by power or noise requirements, necessitating a balance in digital circuit design to achieve design goals.
Innovation Solution
A circuit and method are introduced that utilize a storage circuit with flip-flops and a comparison circuit to deactivate the clock signal when received data has the same logical value as previously stored data, reducing power consumption and improving data setup time by employing clock gating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If dynamic flip-flops are used to reduce data setup time, then data setup time is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic clock gating that adapts to data transition patterns. The clock signal is dynamically enabled or disabled based on whether data changes between consecutive cycles, allowing the system to optimize between speed and power consumption in real-time based on actual data activity
Solution Approach 2:
The system changes the clock signal parameter (from active to inactive state) based on data comparison results. When data remains unchanged, the clock is gated off, effectively changing the operational parameters of the flip-flop to reduce power while maintaining data integrity
2Use of energy by moving object
If clock gating is used to reduce power consumption, then power consumption is reduced, but data setup time may increase
Solution Approach 1:
The patent employs feedback through data comparison between consecutive cycles to control clock gating. The system continuously monitors whether data has changed and uses this feedback to determine whether to enable or disable the clock signal, ensuring that data setup requirements are met while minimizing power consumption
Solution Approach 2:
The comparison circuit performs preliminary evaluation of data changes before the clock edge arrives. By determining in advance whether data has changed, the system can prepare the clock gating state appropriately, ensuring that data setup time requirements are satisfied while avoiding unnecessary clock cycles that would consume power
Data Source
AI summary
Embodiments of a logic path are disclosed that may allow for a reduction in switching power. The logic path may include a storage circuit, a comparison circuit, and a clock gating circuit. The storage circuit may be configured to store received data responsive to a local clock signal. The comparison circuit may be operable to compare the received data to data previously stored in the storage circuit. The clock gating circuit may be configured to generate the local clock signal dependent on a global clock signal, and de-activate the local clock signal dependent upon the results of the comparison performed by the comparison circuit.