Fine-Grained Bandwidth Provisioning in Memory Controllers
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Solution Overview
Problem
Existing quality of service (QoS) logic solutions for dynamic random access memory (DRAM) devices suffer from wide bandwidth variations, limiting software applications to specific types of DRAM and preventing upgrades to faster, cheaper DRAM types without risking application failures.
Innovation Solution
A fine-grained QoS logic system that determines the priority class and bandwidth consumption of each master device, scheduling memory access requests to minimize bandwidth variations by applying a priority-based scheduling mechanism and throttling requests to maintain consistent bandwidth allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If prioritization and rate limiting mechanisms are used for QoS logic, then bandwidth variations are controlled to some extent, but wide bandwidth variations still occur that limit software applications to specific DRAM types
Solution Approach 1:
The patent segments the bandwidth allocation into multiple fine-grained queues, each dedicated to specific master devices or priority classes. This segmentation allows precise control over bandwidth distribution, enabling the system to maintain consistent bandwidth characteristics across different DRAM types while supporting multiple master devices with different bandwidth requirements.
Solution Approach 2:
The patent implements dynamic bandwidth adjustment by continuously monitoring actual bandwidth usage and adjusting queue priorities and allocation in real-time. This dynamic mechanism allows the system to adapt to varying workload conditions and maintain bandwidth consistency regardless of the specific DRAM type being used.
2Reliability
If extensive testing is performed to ensure application reliability under bandwidth variations, then application failures are prevented, but the complexity and time required for system deployment increases
Solution Approach 1:
The patent performs preliminary configuration of priority classes and bandwidth allocation parameters during system initialization, establishing a predetermined scheduling policy that ensures application reliability without requiring extensive runtime testing. The fine-grained queue structure is pre-configured to handle different master devices and priority levels automatically.
Solution Approach 2:
The system implements self-adjusting bandwidth management where the memory controller automatically monitors and regulates bandwidth allocation based on actual usage patterns. This self-service mechanism eliminates the need for manual testing and configuration adjustments, reducing deployment complexity while maintaining application reliability.
3Productivity
If faster, cheaper DRAM types are adopted during later periods of a device lifecycle, then cost and performance are improved, but previously developed software applications fail to run properly due to bandwidth variations
Solution Approach 1:
The patent changes the bandwidth allocation parameters dynamically based on the actual DRAM type and its performance characteristics. By adjusting queue priorities, bandwidth limits, and scheduling policies according to the specific DRAM capabilities, the system maintains software compatibility while enabling the use of faster, cheaper DRAM types during later product lifecycle periods.
Data Source
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AI summary
Systems and methods for applying a fine-grained QoS logic are provided. The system may include a memory controller, the memory controller configured to receive memory access requests from a plurality of masters via a bus fabric. The memory controller determines the priority class of each of the plurality of masters, and further determines the amount of memory data bus bandwidth consumed by each master on the memory data bus. Based on the priority class assigned to each of the masters and the amount of memory data bus bandwidth consumed by each master, the memory controller applies a fine-grained QoS logic to compute a schedule for the memory requests. Based on this schedule, the memory controller converts the memory requests to memory commands, sends the memory commands to a memory device via a memory command bus, and receives a response from the memory device via a memory data bus.