Fine Granularity Flash Translation Layer for NAND Write Performance
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Solution Overview
Problem
NAND flash memories exhibit lower write performance compared to read performance, leading to increased latency and reduced endurance due to the need for numerous write operations during page eviction in SSDs, which limits their effectiveness in handling page faults and caching operations.
Innovation Solution
Implementing a finer granularity Flash Translation Layer (FTL) with delta write engines and logical-to-physical mappings of 64 Byte blocks, rather than traditional 4K page sizes, to reduce write amplification and improve write performance by only writing modified data, and using memory zoning to enhance wear leveling and endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional 4K page size FTL is used for NAND flash memory, then the system can maintain simpler mapping structure, but write amplification increases and write performance deteriorates due to writing entire pages even when only small portions are modified
Solution Approach 1:
The patent segments the traditional 4K page into smaller 64-byte blocks for granular tracking and mapping. Each block can be independently managed, allowing the system to write only modified blocks rather than entire pages. This segmentation enables fine-grained control over write operations, reducing write amplification while maintaining manageable mapping complexity through structured block-level tracking.
Solution Approach 2:
The patent introduces a new dimension of granularity by operating at the 64-byte block level rather than the traditional 4K page level. This dimensional change in the mapping granularity allows the system to selectively write only the necessary portions of data, transforming the write operation from page-level to block-level precision and thereby improving write performance.
2Device complexity
If traditional 4K page size FTL is used, then the mapping overhead is lower, but the number of write operations increases leading to reduced NAND memory endurance
Solution Approach 1:
By segmenting the page into 64-byte blocks, the system can track and write only modified blocks rather than entire pages. This reduces the total number of write operations to NAND memory, directly extending endurance. The mapping overhead increases slightly due to block-level tracking, but this is offset by the significant reduction in write amplification and unnecessary writes.
Solution Approach 2:
The patent implements block-level invalidation and recovery mechanisms where only modified blocks are written to NAND, while unchanged blocks are discarded from write operations. This selective approach recovers write operations that would otherwise be wasted on unchanged data, preserving NAND memory endurance without requiring comprehensive page-level writes.
3Loss of energy
If 64 Byte block granularity FTL is implemented, then write amplification is reduced by writing only modified data, but the mapping structure complexity and memory requirements for L2P tables increase
Solution Approach 1:
The patent segments the L2P mapping structure into block-level entries, allowing precise tracking of only modified 64-byte blocks. This segmentation reduces write amplification by enabling selective writes of only changed blocks rather than entire pages. The increased mapping table size is managed through efficient data structures and zone-based organization, balancing the trade-off between write efficiency and memory overhead.
Solution Approach 2:
The patent transitions from page-level to block-level mapping dimension, creating a more granular L2P structure. This dimensional change enables precise tracking of modified blocks, reducing write amplification. The complexity is managed by organizing mappings in zones and using hierarchical indexing, which structures the increased data volume in a manageable manner.
4Reliability
If zone-based FTL with fine granularity is used, then wear leveling is improved and data is evenly distributed, but the FTL structure and management complexity increases
Solution Approach 1:
The patent segments the NAND memory into multiple zones with independent FTL management, allowing fine-grained wear leveling at the zone level. Each zone maintains its own L2P mappings and can be independently managed, improving wear distribution across the entire memory device. This zone-based segmentation enables more effective load balancing and wear equalization compared to traditional page-level approaches.
Solution Approach 2:
The patent introduces zone-level organization as an additional dimension to the traditional page-level FTL structure. This multi-dimensional organization (zones containing pages containing blocks) enables hierarchical wear leveling and more flexible memory management. The increased complexity is justified by the significant improvement in wear leveling effectiveness and extended memory lifespan.
Data Source
AI summary
A Data Storage Device (DSD) includes a non-volatile memory configured to store data, and control circuitry configured to receive a memory access command from a host to access data in the non-volatile memory. A location is identified in the non-volatile memory for performing the memory access command using an Address Translation Layer (ATL) that has a finer logical-to-physical granularity than a logical-to-physical granularity of a logical block-based file system executed by the host or a granularity based on a memory Input/Output (IO) transaction size of a processor of the host. The non-volatile memory is accessed at the identified location to perform the memory access command.