Fine Line Hard Mask Patterning Beyond Lithography Limits
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Solution Overview
Problem
Current patterning techniques, such as lithography and etching, face limitations in achieving the smallest possible edge-to-edge or end-to-end distance in fine line patterns, which is essential for advanced electronic devices like semiconductor circuits, due to wavelength constraints and challenges in manipulating nanostructures on an industry scale.
Innovation Solution
The method employs directional etching and ion implantation to modify the horizontal profile of patterned hard mask layers, reducing the edge-to-edge distance by selectively etching in a horizontal direction and using ion implantation to harden specific regions, allowing for finer line patterns than achievable with traditional photolithographic and etching methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional photolithographic and etching methods are used, then manufacturing process is simple and well-established, but the edge-to-edge distance in fine line patterns cannot be reduced below a certain limit due to wavelength constraints
Solution Approach 1:
The patterning process is divided into multiple sequential steps: initial lithography to form first patterns, directional etching to form second patterns with reduced edge-to-edge distance, and selective removal of portions. This segmentation allows each step to optimize for its specific function, achieving sub-lithographic dimensions while maintaining process control
Solution Approach 2:
The method performs preliminary lithography and etching to create initial patterns and spacers before the final directional etching step. These preliminary structures serve as templates and protection layers that enable the subsequent directional etching to achieve the desired fine line patterns with precise edge-to-edge distances
2Manufacturing precision
If bottom-up nanostructure growth methods are used, then smaller dimensions can be achieved, but manipulation and alignment of nanostructures into electronic devices is very challenging and time consuming
Solution Approach 1:
The patent replaces the mechanical manipulation of individual nanostructures with a field-based directional etching process. Instead of physically moving and aligning nanostructures, the method uses controlled plasma or ion beams to etch patterns directly in the deposited layer, achieving both small dimensions and high productivity through a scalable industrial process
3Manufacturing precision
If lithography wavelength is reduced to achieve smaller features, then edge-to-edge distance decreases, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from relying solely on optical dimension reduction (shorter wavelength) to using a temporal sequence of patterning steps. By performing multiple etching operations at different times with different mask configurations, the method achieves sub-lithographic dimensions without requiring shorter wavelengths, thus avoiding the complexity associated with advanced lithography tools
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of fine line patterns with dimensions smaller than those achieved by conventional methods, facilitating the production of advanced semiconductor devices with improved resolution and efficiency on an industrial scale.
Implementation Method 1
a directional etching process is performed to etch opposite side portions of a portion of the first hard mask between two gaps from two opposite directions
Implementation Method 2
hardening a sidewall portion of the first hard mask
Data Source
AI summary
A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.