Fine Line Patterns via Spacer Lithography
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Solution Overview
Problem
Current double patterning technologies for forming fine line patterns in semiconductor devices face limitations in achieving narrow pitches smaller than the minimum resolution of photolithography, particularly in scaling and design rule implementation.
Innovation Solution
A method involving the formation of lower and upper linear core structures, spacer layers, and etching processes to create fine line patterns, where the upper hard mask layer is thinned and exposed spacer portions are removed, allowing for the formation of line patterns with narrow spaces using established photolithography and deposition/etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography processes are used, then the process is simple and equipment cost is low, but the minimum line pitch cannot be reduced below the resolution limit
Solution Approach 1:
The patent applies segmentation by dividing the pattern formation into multiple discrete steps: forming mandrels, depositing first spacers, forming second spacers, and performing selective removal. This multi-stage approach enables achieving sub-resolution pitch by breaking down the complex patterning challenge into manageable sequential operations, where each step contributes to the final fine line pattern without requiring advanced photolithography equipment
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical structuring by forming spacer layers that extend vertically from mandrels. This dimensional change allows the use of deposition thickness control to define horizontal pattern dimensions, enabling pitch control through vertical film thickness rather than lateral optical resolution
2Manufacturing precision
If SADP technique is used, then scaling potential is stronger with smaller design rules, but the process development and design flow implementation are less mature
Solution Approach 1:
The patent implements self-service through self-aligned spacer formation where the first and second spacers automatically position themselves relative to the mandrels and each other through conformal deposition. This self-alignment mechanism eliminates the need for additional alignment steps and complex design flow modifications, making the process more mature and easier to manufacture while achieving smaller design rules
Solution Approach 2:
The patent utilizes parameter changes by controlling the thickness of spacer layers through deposition parameters to define the final line width and pitch. By adjusting deposition thickness rather than relying on complex etch selectivity or alignment parameters, the process achieves precise dimensional control with simpler process implementation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively forms fine line patterns with narrow spaces smaller than the minimum photolithography resolution, enhancing the integration density of semiconductor devices without requiring advanced photolithography processes or expensive equipment.
Implementation Method 1
the forming the upper hard mask layer is performed by spin-coating
Implementation Method 2
the thinning the upper hard mask layer is performed by an etch back process
Implementation Method 3
the thinning the upper hard mask layer and the removing the exposed portions of the spacer layer are performed by a dry etching process
Data Source
AI summary
A method of forming fine line patterns of semiconductor devices includes: forming a plurality of lower linear core structures on at least one lower hard mask layer disposed on a target layer; forming a spacer layer on the hard mask layer to cover the lower linear core structures; forming an upper hard mask layer on the spacer layer; thinning the upper hard mask layer to expose potions of the spacer layer; and removing the exposed portions of the spacer layer to form a plurality of line patterns on the lower hard mask layer.