Fine-Pitch Chip Interconnect Layout for Multi-Chip Alignment
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Solution Overview
Problem
Existing interconnection technologies struggle to meet the demands of high bandwidth, low power, good heat dissipation, reliability, and low cost in multi-chip modules, and alignment of components is difficult.
Innovation Solution
The use of interconnect devices with fine-pitch interconnect areas (2 μm-10 μm) and direct-bonded native interconnects (DBI) technology for connecting chips, allowing for high bandwidth signaling without amplification or modification of native signals, and eliminating the need for under-fill and Thru Silicon Vias (TSVs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing interconnection technologies are used in multi-chip modules, then manufacturing is simpler, but bandwidth and power efficiency deteriorate
Solution Approach 1:
The patent introduces an interconnect device as an intermediary component between multiple chips, providing fine-pitch interconnect areas that enable high-bandwidth, low-power communication. This intermediary structure resolves the contradiction by offering a specialized connection interface that achieves superior power efficiency and bandwidth without complicating the overall manufacturing process.
Solution Approach 2:
The patent changes the pitch parameter of interconnect areas to fine-pitch dimensions (2 μm-10 μm), which fundamentally improves power efficiency and bandwidth characteristics. This parameter change enables direct-bonded native interconnects to achieve high-performance electrical characteristics while maintaining manufacturing feasibility through standardized processes.
2Power
If fine-pitch interconnect areas are used for high bandwidth signaling, then bandwidth improves, but alignment precision requirements worsen
Solution Approach 1:
The patent incorporates alignment marks and alignment features directly into the interconnect device structure before chip bonding. These preliminary alignment features enable precise positioning of fine-pitch interconnect areas during the bonding process, resolving the contradiction by providing built-in guidance that simplifies the alignment task despite the tight pitch requirements.
Solution Approach 2:
The patent replaces complex mechanical alignment systems with direct-bonded native interconnect technology that uses material-level bonding and integrated alignment features. This substitution eliminates the need for separate mechanical alignment mechanisms and achieves high precision through the bonding process itself, enabling fine-pitch connections without proportionally increasing alignment difficulty.
3Device complexity
If conventional interconnection methods are used, then device complexity is lower, but thermal performance worsens
Solution Approach 1:
The patent employs composite material structures in the interconnect device, combining different materials with complementary thermal and electrical properties. This composite approach enables simultaneous achievement of high bandwidth signaling and effective heat dissipation without significantly increasing device complexity, as the composite structure is integrated into the interconnect device architecture.
Solution Approach 2:
The interconnect device serves as a thermal intermediary between high-power chips and the heat sink, providing dedicated thermal pathways through its composite material structure. This intermediary function resolves the contradiction by managing heat flow at the interconnect level without requiring complex thermal management systems across the entire multi-chip module.
4Reliability
If direct-bonded native interconnects are used, then reliability improves, but manufacturing complexity worsens
Solution Approach 1:
The patent merges the interconnection function with the substrate function by integrating interconnect areas directly into the interconnect device structure. This merging eliminates separate interconnection layers and bonding steps, achieving high reliability through direct-bonded native interconnects while simplifying the overall manufacturing process by reducing the number of discrete manufacturing operations.
Data Source
AI summary
Techniques are disclosed herein for connecting multiple chips using an interconnect device. In some configurations, one or more interconnect areas on a chip can be located adjacent to each other such that at least a portion of an edge of a first interconnect area is located adjacent to an edge of a second interconnect area. For example, an interconnect area can be located at a corner of a chip such that one or more edges of the interconnect area lines up with one or more edges of an interconnect area of another chip. The chip including at least one interconnect area can also be positioned and directly bonded to the interconnect device using other layouts, such as but not limited to a pinwheel layout. In some configurations more than one interconnect area can be included on a chip.