Fine Pitch Memory Array Formation via Hardmask Segmentation

The patent segments the feature formation process into multiple steps: first forming a patterned layer with relaxed pitch, then using that pattern as a template to define second layers with tighter pitch. This segmentation allows each layer to be formed with appropriate spacing, avoiding edge spreading artifacts while achieving fine final pitch through the combination of layers.

The patent transitions from two-dimensional planar patterning to three-dimensional stacked patterning. By forming multiple layers of features at different vertical positions, the design achieves high horizontal density while maintaining adequate spacing within each layer. The vertical stacking dimension allows tight overall packing without requiring tight horizontal spacing that would cause edge artifacts.

The patent employs self-aligned patterning where previously deposited patterned layers automatically serve as alignment templates for subsequent layers. The first patterned layer defines the positions of second layers without requiring separate mask alignment steps. This self-service approach achieves tight packing and high density while reducing the number of masks needed compared to conventional double-patterning.

The patent replaces sharp cornered square features with rounded or curved feature geometries. By using circular or rounded rectangular patterns instead of sharp squares formed by orthogonal line overlaps, the design eliminates corner-related stacking faults and current leakage paths while maintaining the necessary diode footprint area for proper device operation.