Semiconductor Package Pad Spacing for Fine-Pitch Bonding Reliability
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Solution Overview
Problem
As semiconductor chips become more highly integrated and perform at higher levels, the connection bumps connecting them to package substrates face challenges due to finer pitches, leading to potential electrical shorts and defects during thermal compression bonding processes.
Innovation Solution
A semiconductor package design featuring a package substrate with a redistribution layer and solder mask layer configuration that includes first and second pads, where second pads are positioned on both sides of first pads, and connection bumps are spaced apart from the solder mask layer by a significant distance, ensuring reliable electrical connections and preventing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If connection bumps are arranged at finer pitch to support higher integration and performance, then the semiconductor chip's functionality and integration level are improved, but the risk of electrical shorts and defects during thermal compression bonding increases
Solution Approach 1:
The patent introduces a spacer structure as an intermediary element positioned between the connection bumps and the solder mask layer. This spacer maintains a controlled distance, preventing direct contact that could cause electrical shorts while still allowing fine-pitch arrangement of connection bumps for high integration. The spacer acts as a mediating structure that enables both fine pitch and reliability simultaneously.
Solution Approach 2:
The patent applies different properties to different regions: the spacer provides insulation and spacing in critical areas where electrical shorts could occur, while the connection bumps maintain fine pitch in areas where high integration is needed. This localized differentiation of properties allows the system to achieve both fine pitch arrangement and electrical connection reliability.
2Area of stationary object
If connection bumps are positioned closer to the solder mask layer to maximize space utilization, then the device area is reduced, but the likelihood of defects during thermal compression bonding increases
Solution Approach 1:
The spacer serves as an intermediary that enables close positioning of connection bumps to the solder mask layer while maintaining a safe distance through the spacer's physical presence. This allows maximum space utilization without compromising bonding precision, as the spacer prevents direct contact that would cause defects.
3Quantity of substance
If the distance between connection bumps is reduced for fine pitch arrangement, then the integration density is improved, but the manufacturing precision and reliability of thermal compression bonding deteriorate
Solution Approach 1:
The spacer acts as a standardized intermediary component that provides consistent spacing between connection bumps. This enables fine pitch arrangement (high integration density) while maintaining reliable manufacturing precision, as the spacer ensures uniform gaps that prevent bonding defects even at reduced distances.
Solution Approach 2:
The patent changes the spacing parameter by introducing the spacer, which maintains a controlled distance between connection bumps. This parameter modification enables fine pitch arrangement while preserving bonding precision, as the spacer ensures minimum safe distances are maintained regardless of how close the bumps are arranged.
Data Source
AI summary
A semiconductor package includes a package substrate including a redistribution layer including first pads and second pads on an upper surface thereof and a solder mask layer having an opening exposing the first pads entirely and exposing at least portion of each of the second pads, a semiconductor chip on the upper surface of the package substrate and including connection pads electrically connected to the redistribution layer, connection bumps below the semiconductor chip and connecting the connection pads to the first pads, and a non-conductive film layer between the semiconductor chip and the package substrate, wherein the second pads are respectively disposed on both sides of the first pads at least in a first direction, and the connection bumps are spaced apart from the second pads and the solder mask layer in the first direction.