Fine Pitch Traces for Solid State Diffusion Bonding
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high-density interconnects with fine pitch interconnection, particularly below 20 μm, due to limitations in traditional semi-additive and subtractive methods, which struggle with maintaining the top and bottom trace ratio and require precise control of temperature and pressure to avoid damage to semiconductor materials.
Innovation Solution
A semiconductor package is created using a flexible substrate with traces comprising five different conductive materials, optimized for both diffusion bonding and soldering, formed through a process involving electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) plating, allowing for thermo-compressive bonding and enabling bond pitches below 16 μm with a trace aspect ratio greater than 1.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional semi-additive and subtractive methods are used to reduce trace pitch, then manufacturing process is simpler, but trace pitch cannot be reduced below 20 μm and top/bottom trace ratio cannot be maintained as 1
Solution Approach 1:
The patent changes the fundamental manufacturing approach from semi-additive or subtractive methods to a wrap-around plating process with controlled aspect ratios. By parameterizing the trace geometry (top width, bottom width, height) and controlling the aspect ratio to be greater than 1, the process achieves sub-20 μm pitch while maintaining manufacturing feasibility through electroless copper deposition and selective etching.
Solution Approach 2:
The patent employs a multi-layer composite structure consisting of dielectric material layers, conductive trace layers, and metallic bump structures. The traces are formed as three-dimensional structures with specific top and bottom widths, creating a composite geometry that enables fine pitch interconnection while maintaining structural integrity and electrical performance.
2Strength
If bonding temperature and pressure are increased to achieve strong bonding, then bond strength is improved, but semiconductor materials may be damaged
Solution Approach 1:
The patent introduces a deformable layer as an intermediary between the trace and the bonding interface. This layer absorbs and distributes the bonding pressure, enabling strong bonding at lower temperatures and pressures that do not damage the semiconductor materials. The deformable layer acts as a buffer that protects the brittle semiconductor structures from direct mechanical stress.
Solution Approach 2:
The patent optimizes the bonding parameters by using a deformable layer that enables bonding at reduced temperature and pressure conditions. The layer's mechanical properties are specifically engineered to allow deformation under bonding pressure, facilitating intimate contact between bonding surfaces without transmitting excessive stress to the semiconductor materials.
3Productivity
If bond pitch is reduced to 10 μm width with 10 μm spacing, then interconnection density is improved, but maintaining uniform pressure and proper surface formation becomes difficult
Solution Approach 1:
The patent applies local quality by creating traces with different top and bottom widths, and using a deformable layer with specific local mechanical properties. The trace geometry is optimized locally at each bonding site to ensure proper pressure distribution and surface formation, even at reduced pitch. The deformable layer provides localized compliance that ensures uniform pressure across the bonding interface.
Solution Approach 2:
The patent performs preliminary deformation of the deformable layer during the bonding process to ensure proper surface formation before final bonding occurs. This preliminary action prepares the bonding surface to receive uniform pressure distribution, enabling successful bonding at fine pitch dimensions where pressure uniformity is critical.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables reliable and high-density semiconductor packaging with improved electrical connections and thermal performance, suitable for applications in various technologies, including flip-chip assembly, by providing strong and uniform bonding while maintaining the integrity of semiconductor materials.
Implementation Method 1
electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) plating
Implementation Method 2
Immersion Gold (ENEPIG) plating
Implementation Method 3
Diffusion bonding is a method of joining metallic or non-metallic materials. This bonding technique is based on the atomic diffusion of elements at the joining interface
Implementation Method 4
a deformable layer so that under pressure the plastic deformation of that layer operates to bring the interface to the bonding temperature more quickly and to enhance diffusion
Implementation Method 5
The deformable layer must provide the requisite electrical properties
Implementation Method 6
Thermo-compression bonding has a predicted application in flip chip assembly using gold bumps
Implementation Method 7
Creep mechanism allows a material flow to produce full intimate contact at the joint interface as required for diffusion bonding
Data Source
AI summary
A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising five different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.