Fine Redistribution Pattern Layout for Compact Semiconductor Packaging
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving compact size and reliability due to limitations in redistribution pattern design and fabrication methods, which affect the electrical connectivity and thermal management of semiconductor chips.
Innovation Solution
The development of a semiconductor package with redistribution patterns in a dielectric layer, featuring a line part and a via part, where the line part has a central portion with minimum thickness and edge portions with maximum thickness, and a convex bottom surface, along with a thermal radiation structure for improved thermal management, is proposed. The fabrication method involves forming a hardmask layer, photoresist pattern, and anisotropic etching to create trenches and via holes, followed by metal deposition and planarization to form redistribution patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional redistribution patterns with uniform thickness are used, then fabrication is simpler, but electrical connectivity and thermal management are insufficient
Solution Approach 1:
The redistribution pattern is designed with non-uniform thickness, where the first portion (under chip pads) has greater thickness than the second portion (interconnect regions). This local variation optimizes electrical connectivity and thermal management at critical locations while maintaining simpler structures elsewhere, resolving the contradiction between reliability and device complexity.
2Volume of moving object
If compact-sized packages are achieved through fine redistribution patterns, then package size is reduced, but fabrication precision requirements increase
Solution Approach 1:
The redistribution pattern is segmented into distinct portions with different thicknesses - a first portion with greater thickness for electrical connectivity and a second portion with lesser thickness for compact routing. This segmentation allows compact package design while managing fabrication precision requirements through defined structural zones rather than uniform fine features throughout.
Solution Approach 2:
By applying different thickness characteristics to different portions of the redistribution pattern, the design achieves compact overall size while maintaining adequate thickness in critical areas for reliable electrical connectivity, thus balancing package size reduction with manufacturability.
3Temperature
If uniform thickness redistribution patterns are used, then manufacturing is easier, but thermal management efficiency is reduced
Solution Approach 1:
The redistribution pattern incorporates a first portion with greater thickness positioned under chip pads and heat-generating regions, enhancing thermal management where needed. The second portion has lesser thickness for compact routing. This localized thickness variation improves heat dissipation without significantly complicating the overall manufacturing process.
Data Source
AI summary
Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.