3D FinFET Contact Structure for Lower Resistance Interfaces
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, increasing integration density leads to challenges such as higher resistance and reduced performance in FinFETs due to smaller contact areas and work function differences between materials.
Innovation Solution
The formation of gate contacts and source/drain contacts with increased surface areas, achieved by exposing sidewalls and modifying top surfaces to convex or concave shapes, along with doping to reduce work function differences, enhances the interface area and performance by improving contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but contact area decreases leading to higher resistance and reduced performance
Solution Approach 1:
The patent transitions from planar contact interfaces to three-dimensional contact structures with exposed sidewalls. The first and second conductive features are formed with vertical sidewalls that extend laterally beyond the channel region, creating additional contact surfaces. This dimensional change from 2D to 3D contact geometry increases the effective contact area without increasing the footprint area, thereby reducing contact resistance while maintaining high integration density.
Solution Approach 2:
The patent employs curved or angled sidewalls in the contact structures rather than purely vertical walls. The conductive features have rounded corners and curved surfaces that increase the contact area with the doped region. This curvature principle allows for larger contact surfaces within the same lateral dimensions, improving electrical coupling and reducing resistance.
2Productivity
If contact area is reduced to increase integration density, then more devices fit in a given area, but work function differences between materials become more significant
Solution Approach 1:
The patent employs a composite contact structure consisting of multiple conductive features with different materials and doping types. The first conductive feature has a first doping type while the second conductive feature has a second doping type opposite to the first. This composite structure allows for better work function matching with the underlying semiconductor region, reducing Schottky barrier effects and improving carrier injection efficiency.
Solution Approach 2:
The patent applies different doping types and material compositions to different regions of the contact structure. The first conductive feature is doped with one type of impurity while the second conductive feature is doped with the opposite type. This local differentiation optimizes the electrical properties at each contact interface, ensuring proper work function matching and reducing contact resistance.
3Ease of manufacture
If conventional planar contact interfaces are used, then manufacturing is simpler, but contact resistance is higher due to limited interface area
Solution Approach 1:
The patent divides the contact structure into multiple segmented conductive features instead of using a single planar contact. The first and second conductive features are formed as separate entities with distinct doping types and spatial arrangements. This segmentation increases the total contact area and improves electrical coupling while maintaining a relatively simple manufacturing process that can be integrated into existing fabrication sequences.
Data Source
AI summary
An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.