FinFET Active Contact Air-Gap Layout for Sub-20 Nm Reliability
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improvements in semiconductor devices to maintain high performance.
Innovation Solution
The semiconductor device incorporates PMOSFET and NMOSFET regions with specific structural features, including active patterns, channel patterns, source/drain patterns, gate electrodes, air gaps, and via connections, to enhance electrical characteristics and mitigate scaling issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern sizes, then device density and integration are improved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar 2D MOS-FET structures to three-dimensional FinFET structures with vertical channels. The channel extends vertically along the fin structure, adding a vertical dimension to current flow. This dimensional change increases the effective channel area and control gate coverage without increasing the lateral footprint, thereby maintaining device density while improving operational characteristics through enhanced gate control and reduced short-channel effects
Solution Approach 2:
The patent implements nested contact structures where lower vias are positioned within or adjacent to air gaps that are themselves adjacent to conductive patterns. The air gap structure nests the lower via while providing electrical isolation. This nested arrangement allows multiple functional elements to occupy overlapping or adjacent spatial regions, increasing device density and enabling complex interconnect schemes without proportionally increasing the lateral device footprint
2Ease of manufacture
If conventional contact structures are used in scaled devices, then manufacturing is simpler, but electrical performance and defect rates worsen
Solution Approach 1:
The patent introduces air gaps as intermediary structures between conductive patterns and underlying substrates or other conductive elements. These air gaps serve as dielectric mediators that provide electrical isolation while allowing close spatial proximity of conductive elements. The air gaps can be formed through selective removal of sacrificial materials, enabling precise positioning and controlled formation without requiring complex direct patterning of insulating layers
Solution Approach 2:
The patent employs parameter changes in the contact structure formation process, including varying the depth, width, and positioning of lower vias relative to air gaps and conductive patterns. The dimensions and spatial relationships of these structures are optimized to achieve desired electrical characteristics such as reduced parasitic capacitance, improved current density distribution, and enhanced thermal management while maintaining manufacturability through standard semiconductor fabrication processes
Data Source
AI summary
A semiconductor device may include PMOSFET and NMOSFET regions spaced apart from each other on a substrate, first and second active patterns provided on the PMOSFET and NMOSFET regions, respectively, a first channel pattern on the first active pattern, a source/drain pattern electrically connected to the first channel pattern, an active contact electrically connected to the source/drain pattern, the active contact including a first conductive pattern and a first barrier pattern enclosing a portion of a side surface and a bottom surface of the first conductive pattern, a gate electrode extending in a direction crossing the first channel pattern, a gate contact electrically connected to the gate electrode, an air gap provided on the first barrier pattern and between the gate contact and the first conductive pattern, and a lower via provided on the active contact. The lower via may be adjacent to the air gap.