FinFET Active Fin Stress Engineering for Carrier Mobility
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Solution Overview
Problem
Conventional semiconductor devices face challenges in enhancing hole mobility in PMOS regions and electron mobility in NMOS regions at low voltage, particularly in fin field effect transistors (FinFETs), which affects their structural integrity and driving current performance.
Innovation Solution
A method of manufacturing semiconductor devices that involves forming compressive stress in the PMOS region using a SiGe epitaxial layer and tensile stress in the NMOS region using a nickel-platinum silicide layer to enhance mobility, achieved by creating specific recesses and silicide layers in the active fins of the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional field effect transistors are used, then manufacturing is simpler, but hole mobility in PMOS regions and electron mobility in NMOS regions cannot be enhanced at low voltage
Solution Approach 1:
The patent applies different stress conditions to different regions: compressive stress is applied to PMOS channel regions to enhance hole mobility, while tensile stress is applied to NMOS channel regions to enhance electron mobility. This local differentiation of stress conditions resolves the contradiction by tailoring the device structure to specific functional requirements in different regions.
Solution Approach 2:
The patent uses composite material structures including stress layers with specific compositions (such as SiGe for compressive stress and materials providing tensile stress) combined with channel regions. These composite structures enable simultaneous enhancement of hole and electron mobility in different regions, overcoming the limitations of conventional single-material transistor structures.
2Reliability
If stress layers are added to enhance carrier mobility, then performance improves, but manufacturing process complexity increases
Solution Approach 1:
The stress layers are formed preliminarily during the manufacturing process, integrated with the formation of active fins and gate structures. By incorporating stress layer formation into existing manufacturing steps rather than adding separate post-processing steps, the patent enhances carrier mobility while minimizing increases in manufacturing process complexity.
Solution Approach 2:
The patent merges the formation of stress layers with the formation of active fins and gate structures into an integrated manufacturing process. Multiple functions (creating active fins, forming stress layers, preparing gate structures) are combined into a unified process flow, reducing the overall manufacturing complexity despite the addition of stress enhancement features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases hole mobility in PMOS regions and electron mobility in NMOS regions, improving the overall performance and structural integrity of the semiconductor devices by optimizing carrier mobility at low voltage.
Implementation Method 1
forming a stress layer that provides compressive stress to increase hole mobility in a channel of a PMOS region
Implementation Method 2
forming a stress layer that provides tensile stress to increase electron mobility in a channel of an NMOS region
Implementation Method 3
forming a first epitaxial layer in the first recess
Data Source
AI summary
Provided is a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor includes preparing a substrate on which a first region and a second region are defined, forming a first active fin and a second active fin in the first and second regions, respectively, forming a first gate structure and a second gate structure on the substrate in a direction that crosses the first and second active fins, forming a first recess in the first active fin that is adjacent to one side surface of the first gate structure, forming a first epitaxial layer in the first recess, forming a first silicide layer on the first epitaxial layer, forming a second recess in the second active fin that is adjacent to one side surface of the second gate structure, and forming a second silicide layer in the second recess, wherein the second silicide layer includes nickel (Ni) and platinum (Pt).