FinFET structure with controlled air gaps
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Solution Overview
Problem
Existing semiconductor technologies face issues with parasitic capacitance and bridging (leakage) at advanced technology nodes, leading to circuit performance degradation and reliability concerns, particularly with smaller feature sizes.
Innovation Solution
The introduction of controlled air gaps within the interconnection structure of FinFETs, achieved through precise etching and deposition processes, including the formation of air gaps in isolation features to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interconnection structures are used at advanced technology nodes, then circuit integration is achieved, but parasitic capacitance increases leading to performance degradation
Solution Approach 1:
The patent introduces air gaps (porous structures) within the interconnection layout, specifically forming void regions between adjacent conductive features. These air gaps replace solid dielectric material with low-permittivity air, directly reducing parasitic capacitance between interconnection elements while maintaining the conductive routing functionality.
Solution Approach 2:
The patent extracts material to create air gaps by removing dielectric material from specific regions between conductive interconnection features. This extraction process forms void spaces that reduce capacitive coupling, effectively taking out the harmful capacitive interaction while preserving the necessary electrical connections.
2Productivity
If feature sizes are reduced to advance technology nodes, then device density increases, but parasitic capacitance deteriorates further
Solution Approach 1:
The patent applies local quality by creating air gaps only in specific regions between adjacent conductive features where parasitic capacitance is most problematic, while maintaining solid dielectric structures in other areas. This localized approach reduces capacitance at critical interfaces without compromising overall device density or requiring global structural changes.
Data Source
AI summary
The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.