FinFET Air-Gap Contact Structure to Cut Gate Contact Capacitance
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the integration density of electronic components increases, but this leads to challenges such as increased capacitance between the gate stack and contacts in FinFET devices, which can limit high-speed operation and lead to electrical shorts due to conductive material entering air gaps.
Innovation Solution
The formation of air gaps surrounding the source/drain epitaxial regions in FinFET devices with a low dielectric constant, combined with an etch stop layer that seals these gaps to prevent conductive material from entering, reducing leakage and electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but capacitance between gate stack and contacts increases limiting high-speed operation
Solution Approach 1:
An air gap is introduced as an intermediary structure between the gate stack and the contact. This air gap acts as a mediator that reduces the parasitic capacitance between these two components, enabling high-speed operation while maintaining high integration density. The air gap is formed by removing mandrel material, creating a void space that electrically isolates the gate stack from the contact.
Solution Approach 2:
The air gap structure utilizes a void or porous space between the gate stack and contact. This porous structure (empty space) reduces the dielectric constant in the region between gate and contact, thereby reducing capacitance and improving high-speed performance while allowing continued scaling for high integration density.
2Reliability
If air gaps are formed to reduce capacitance, then high-speed operation is enhanced, but conductive material may enter the gaps causing electrical shorts
Solution Approach 1:
The mandrel structure is formed and positioned in advance before the air gap is created. This preliminary structure serves as a template that defines the air gap geometry and provides a barrier during subsequent processing steps. The mandrel is removed after serving its protective function, having already prevented conductive material from entering the gap region during deposition processes.
Solution Approach 2:
The mandrel acts as a protective cushion or barrier placed beforehand to prevent harmful conductive material from entering the air gap. This preliminary protective structure absorbs or blocks potential contamination during the deposition of conductive materials, ensuring the air gap remains clean and electrically isolated.
3Productivity
If minimum feature size is continuously reduced, then integration density increases, but additional problems arise that limit device performance
Solution Approach 1:
The air gap structure introduces a vertical dimension element between the gate stack and contact, creating a three-dimensional configuration rather than a simple planar layout. This vertical separation via air gap reduces capacitance without increasing lateral footprint, enabling continued scaling and high integration density while maintaining device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces capacitance between the gate stack and contacts, enhancing high-speed operation and reliability by minimizing the chance of electrical shorts, while maintaining device performance.
Implementation Method 1
air gaps surrounding contacts to the source/drain epitaxial regions can reduce capacitance between the gate stack and the contacts
Implementation Method 2
an etch stop layer that seals these gaps to prevent conductive material from entering
Data Source
AI summary
A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the spacer, and the source/drain region; a contact plug extending through the ILD and contacting the source/drain region; a dielectric layer including a first portion on a top surface of the ILD and a second portion extending between the ILD and the contact plug, wherein a top surface of the second portion is closer to the substrate than the top surface of the ILD; and an air gap between the spacer and the contact plug, wherein the second portion of the dielectric layer seals the top of the air gap.