FinFET Air-Gap Contact Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing methods for forming air gaps between source/drain contacts and neighboring metal gate structures in FinFETs are prone to damage during the formation of S/D contacts, leading to potential filling of the air gaps with conductive material and increased parasitic capacitance, which is not adequately addressed by current techniques.
Innovation Solution
A method involving the formation of air gaps between metal gate structures and S/D features, utilizing selective etching processes to maintain the integrity of the air gaps and subsequent deposition of dielectric layers to prevent conductive material infiltration, followed by the formation of silicide layers and conductive contacts, ensuring precise alignment and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If air gaps are formed between metal gate structures and S/D contacts, then parasitic capacitance is reduced, but the air gaps are prone to damage during S/D contact formation
Solution Approach 1:
A seal layer is formed over the air gap before forming the S/D contact. This preliminary protective action prevents conductive material from infiltrating the air gap during subsequent processing steps, thereby maintaining the integrity of the air gap while still achieving the parasitic capacitance reduction benefit
Solution Approach 2:
The seal layer acts as an intermediary protective barrier between the air gap and the conductive material used to form S/D contacts. This intermediate layer prevents direct contact between the conductive material and the air gap, eliminating the harmful effect of material infiltration while preserving the beneficial low-capacitance property
2Manufacturing precision
If selective etching processes are used to maintain air gap integrity, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The seal layer is deposited conformally over the air gap structure before S/D contact formation. This preliminary protective layer simplifies subsequent processing by preventing the need for complex selective etching steps to protect the air gap, while still enabling precise S/D contact placement
Solution Approach 2:
The conformal deposition of the seal layer changes the physical parameters of the air gap region, creating a protected environment that maintains the air gap's dimensions and position accuracy without requiring additional complex process controls
Data Source
AI summary
A method includes providing a workpiece including a gate structure (MG), a first spacer along a sidewall of the MG, a second spacer along a sidewall of the first spacer, and a source/drain (S/D) feature adjacent to the second spacer. The method further includes forming a contact trench over the S/D feature, removing the second spacer to form an air gap between the MG and the S/D feature, depositing a first dielectric layer over the S/D feature and partially filling the air gap, removing a portion of the first dielectric layer to expose a central portion of a top surface of the S/D feature while a side portion of the top surface of the S/D feature remains under the first dielectric layer, forming an S/D contact in the contact trench, removing the first dielectric layer to extend the air gap, and depositing a second dielectric layer over the air gap.