FinFET Fill Structure With Air Gaps for Lower Parasitic Capacitance
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Solution Overview
Problem
The existing fill structures in semiconductor devices with finFETs exhibit undesirable parasitic capacitances due to their dielectric constant, which adversely impacts device performance by increasing RC time delay.
Innovation Solution
The introduction of air gaps within the fill structures, which have a dielectric constant of about 1, reduces the overall dielectric constant of the fill structure by 20% to 50% compared to fill structures with only SiN-based dielectric materials. This is achieved by depositing a SiN-based dielectric material at a first deposition rate to form the air gap, followed by depositing the material at a second, higher deposition rate to seal the air gap and fill the isolation trench.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fill structures are made with SiN-based dielectric materials to provide electrical isolation, then isolation effectiveness is improved, but parasitic capacitance increases due to high dielectric constant
Solution Approach 1:
The fill structure incorporates air gaps (porous regions) within the dielectric material to reduce the overall dielectric constant. The air gaps create a composite structure where the effective dielectric constant is lowered from the original SiN value to between 2.7 and 3.6, thereby reducing parasitic capacitance while maintaining electrical isolation functionality
Solution Approach 2:
The fill structure uses a composite material system combining SiN-based dielectric material with air gaps. This composite approach allows the structure to maintain the electrical isolation properties of the dielectric material while the air gaps contribute low dielectric constant regions, achieving a balance between isolation effectiveness and parasitic capacitance reduction
2Loss of time
If air gaps are introduced to reduce dielectric constant and parasitic capacitance, then RC time delay is reduced, but etch back and damage may occur during subsequent processes
Solution Approach 1:
A protective cap layer is deposited over the air gaps before subsequent etching processes. This cap layer acts as a cushioning protective barrier that prevents etch back into the air gaps and protects the fill structure from damage during manufacturing processes, while still allowing the air gaps to function in reducing parasitic capacitance
3Productivity
If deposition rate is increased to seal air gaps efficiently, then manufacturing productivity is improved, but deposition uniformity and air gap quality may deteriorate
Solution Approach 1:
The deposition process uses periodic alternation between low deposition rate phases (for forming and sealing air gaps with quality control) and high deposition rate phases (for bulk material deposition). This periodic switching optimizes both air gap quality and overall manufacturing efficiency by allocating different deposition rates to different functional requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The incorporation of air gaps in the fill structures effectively reduces parasitic capacitance, thereby improving device performance by minimizing RC time delay, while also preventing etch back and damage to the fill structure during subsequent processes.
Implementation Method 1
depositing a SiN-based dielectric material at a first deposition rate to form the air gap
Implementation Method 2
depositing the material at a second, higher deposition rate to seal the air gap and fill the isolation trench
Data Source
AI summary
The present disclosure describes a semiconductor device with a fill structure. The semiconductor structure includes first and second fin structures on a substrate, an isolation region on the substrate and between the first and second fin structures, a first gate structure disposed on the first fin structure and the isolation region, a second gate structure disposed on the second fin structure and the isolation region, and the fill structure on the isolation region and between the first and second gate structures. The fill structure includes a dielectric structure between the first and second gate structures and an air gap enclosed by the dielectric structure. The air gap is below top surfaces of the first and second fin structures.