FinFET Air Gap Isolation for Lower Parasitic Capacitance
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Solution Overview
Problem
As integrated circuit technologies progress towards smaller technology nodes, parasitic capacitance between dielectric components in semiconductor devices increases, leading to lower device speed and complexity in processing, with existing methods not being entirely satisfactory in reducing parasitic capacitance.
Innovation Solution
The method involves forming an air gap along gate spacers and around fins in semiconductor devices to reduce parasitic capacitance, which includes creating a semiconductor device with three-dimensional nanostructure FETs, forming a multi-layer stack of alternating non-channel and channel layers, and using etching processes to create openings for a metal gate stack, followed by forming dielectric helmets and spacers to isolate the gate stack, ultimately replacing dummy gate stacks with metal gate stacks and forming an air gap between the gate spacer and dielectric features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dielectric components are disposed between active device regions to meet design requirements, then device functionality is maintained, but parasitic capacitance increases leading to lower device speed
Solution Approach 1:
The patent extracts the harmful dielectric material between active device regions and replaces it with air gaps. By removing the solid dielectric component that causes parasitic capacitance and substituting it with air (which has minimal dielectric constant), the parasitic capacitance is significantly reduced while maintaining the necessary physical separation between device regions.
Solution Approach 2:
The patent changes the dielectric parameter (dielectric constant) of the material between active device regions from a high-value solid dielectric to air with a dielectric constant close to 1. This parameter change directly reduces parasitic capacitance and improves device speed performance.
2Productivity
If geometry size is decreased to increase functional density, then production efficiency increases and costs decrease, but parasitic capacitance increases and device speed decreases
Solution Approach 1:
The patent applies local quality by introducing air gaps specifically in the regions between active device regions where parasitic capacitance is problematic, while maintaining the scaled-down geometry elsewhere. This localized modification allows continued scaling for productivity while addressing the speed degradation caused by reduced separation distances.
3Area of moving object
If separation distances between active device regions are reduced to meet smaller technology nodes, then functional density increases, but parasitic capacitance increases leading to lower device speed
Solution Approach 1:
The patent extracts the harmful dielectric material from the regions between active device regions and replaces it with air gaps. This extraction allows closer spacing of active devices (increasing functional density) while eliminating the source of parasitic capacitance that would otherwise limit device speed.
4Object-affected harmful factors
If existing methods are used to reduce parasitic capacitance, then some improvement is achieved, but they are not entirely satisfactory in all aspects
Solution Approach 1:
The patent employs self-aligned processes where the air gaps are formed automatically during the fabrication sequence without requiring additional complex processing steps. The gate spacers and dielectric helmets self-align to create the air gap regions, eliminating the need for separate alignment and patterning operations that would increase device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance without compromising other design requirements, improving device performance and scaling capabilities by creating an air gap that isolates the metal gate stack from the source/drain features, thereby enhancing the semiconductor device's speed and reliability.
Implementation Method 1
parasitic capacitance of dielectric components disposed between active device regions may have serious bearings on the overall performance of an IC device
Data Source
AI summary
A semiconductor structure includes a substrate, a semiconductor fin-shaped structure protruding from the substrate and extending lengthwise along a first direction, an isolation feature disposed over the substrate and adjacent to the semiconductor fin-shaped structure and extending lengthwise along the first direction, a metal gate stack disposed over a channel region of the semiconductor fin-shaped structure and extending lengthwise along a second direction perpendicular to the first direction, a gate spacer disposed along a sidewall of the metal gate stack and along a sidewall of the semiconductor fin-shaped structure, a source/drain feature disposed over a source/drain region of the semiconductor fin-shaped structure and adjacent to the metal gate stack, a dielectric layer disposed over the source/drain feature, and an air gap disposed between the gate spacer and the dielectric layer along the first direction and wrapping around the semiconductor fin-shaped structure.