FinFET Air Gap Fabrication for Parasitic Capacitance Reduction
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Solution Overview
Problem
As transistors shrink in size and are integrated more densely on chips, parasitic capacitance between conductive materials increases, leading to electrical isolation challenges in semiconductor devices.
Innovation Solution
A method of fabricating fin field effect transistors (FinFETs) that involves forming a fin structure on a substrate, creating a gate pattern and source/drain electrodes, and introducing an air gap between them by removing a sacrificial layer through a capping layer, which helps control parasitic capacitance by defining precise thickness and width of the air gap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are shrunk in size and integrated more densely, then transistor integration density is improved, but parasitic capacitance between conductive materials increases
Solution Approach 1:
The patent extracts the harmful conductive material between the gate electrode and source/drain electrode by forming an air gap. The sacrificial layer is removed to create a void space that eliminates the parasitic capacitance-causing conductive material, while preserving the essential electrical connections through the gate pattern and source/drain electrodes.
Solution Approach 2:
The patent applies local quality by creating an air gap specifically in the region between the gate electrode and source/drain electrode where parasitic capacitance occurs, while maintaining conductive material in other necessary regions. The blocking layer is selectively formed to cover only the gate pattern and source/drain electrode, leaving the air gap region open.
2Reliability
If air gap is formed to reduce parasitic capacitance, then electrical isolation is improved, but device structure complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the sacrificial layer before creating the air gap. The sacrificial layer is deposited and patterned in advance to define the future air gap location and dimensions. The blocking layer is also formed preliminarily to protect the gate and source/drain electrodes during subsequent processing steps.
Solution Approach 2:
The patent uses the sacrificial layer as an intermediary element that temporarily occupies the space where the air gap will eventually be formed. This intermediary layer simplifies the fabrication process by providing a structured template that can be easily removed later, rather than attempting to create the air gap directly through complex etching or deposition processes.
3Object-generated harmful factors
If precise thickness and width of air gap are controlled, then parasitic capacitance reduction is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses the sacrificial layer as a physical template or copy of the desired air gap structure. The sacrificial layer is formed with the exact thickness and width specifications needed for the final air gap, allowing precise dimensional control to be transferred from the sacrificial layer formation process to the final air gap structure.
Solution Approach 2:
The patent controls air gap dimensions by changing the parameters of the sacrificial layer formation process. The thickness and width of the sacrificial layer are controlled through deposition conditions and photolithography parameters, which are then transferred to the air gap when the sacrificial layer is removed.
Data Source
AI summary
A method of fabricating a fin field effect transistor (FinFET) is provided as follows. A fin structure is formed on a substrate. A gate pattern and a source/drain (S/D) electrode are formed on the fin structure. The gate pattern and the S/D electrode are spaced apart from each other. A blocking layer is on the fin structure to cover the gate pattern and the S/D electrode. A sacrificial pattern is formed on the blocking layer and between the gate pattern and S/D electrode. The sacrificial pattern has a first thickness and a first width. A capping layer is formed on the sacrificial layer. An air gap is formed by removing the sacrificial layer through the capping layer. The air gap is formed between the gate pattern and the S/D electrode and has the first thickness and the first width.