3D FinFET Air Gap Reduces Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices become highly integrated, the decrease in channel width of metal-oxide-silicon field effect transistors (MOSFETs) leads to reduced driving current, affecting operation speed and data sensing margin, necessitating improved alternating current performance.
Innovation Solution
A semiconductor device with a three-dimensional channel region and a method of fabrication that includes a gate electrode crossing over a semiconductor fin, impurity regions, and interlayer dielectric layers to define air gaps, reducing fringing field capacitance and parasitic capacitance through a specific structure and process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel width of MOSFET is decreased to achieve high integration, then the device density is improved, but the driving current amount is reduced
Solution Approach 1:
The patent transitions from planar channel structure to three-dimensional channel structure by forming channels along the side walls of sacrificial fins. This vertical/dimensional extension allows the channel length to increase without reducing channel width, maintaining driving current while achieving higher device density through increased transistor count per unit area.
Solution Approach 2:
The patent forms channels that are nested around the sacrificial fin structure, with channels extending along the side walls. This nested configuration allows multiple channels to be packed in a compact space, increasing device density while each channel maintains sufficient width for adequate driving current.
2Productivity
If the channel width of MOSFET is decreased to achieve high integration, then the device density is improved, but the operation speed is reduced
Solution Approach 1:
The three-dimensional channel structure extends vertically along the side walls of sacrificial fins, allowing channels to be stacked and packed in three dimensions. This increases device density while each channel maintains sufficient width for high operation speed, as the channel width is not reduced but rather the spatial arrangement is optimized.
3Productivity
If the channel width of MOSFET is decreased to achieve high integration, then the device density is improved, but the data sensing margin is reduced
Solution Approach 1:
By forming three-dimensional channels along the side walls of sacrificial fins, the patent increases device density through vertical stacking and compact spatial arrangement. The channel width is maintained at adequate levels, ensuring sufficient driving current difference between on and off states, which preserves data sensing margin for reliable memory operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances alternating current performance by minimizing fringing field capacitance and parasitic capacitance, thereby improving the operation speed and data sensing margin of semiconductor devices.
Implementation Method 1
making it possible to improve alternating current performance by minimizing fringing field capacitance and parasitic capacitance
Implementation Method 2
making it possible to improve alternating current performance by minimizing fringing field capacitance and parasitic capacitance
Data Source
AI summary
Provided is a semiconductor device, which includes a gate electrode crossing over a semiconductor fin disposed on a substrate, a gate dielectric layer disposed between the gate electrode and the semiconductor fin, a channel region having a three dimensional structure defined in the semiconductor fin under the gate electrode, impurity regions disposed in the semiconductor fin at both sides of the gate electrode and spaced apart from the gate electrode, a first interlayer dielectric layer covering an entire surface of the substrate, except for the gate electrode, first contact plugs passing through the first interlayer dielectric layer and contacting the impurity regions, and a second interlayer dielectric layer covering the gate electrode and partially filling a space between the gate electrode and the impurity regions to define an air gap between the gate electrode and the impurity regions.