FinFET Source/Drain Air-Gap Structure for Low-Capacitance Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices scale down, there is a need to reduce capacitance and ensure electrical stability between contacts, while maintaining performance and reliability.
Innovation Solution
The semiconductor device incorporates fin-shaped patterns on a substrate with field insulating films covering their sidewalls, and source/drain patterns made of silicon-germanium that include epitaxial regions and connection semiconductor regions, with air gaps defined between the source/drain patterns and the field insulating films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pitch size of the semiconductor device is decreased to increase density, then device density is improved, but capacitance increases and electrical stability between contacts deteriorates
Solution Approach 1:
The patent introduces air gaps in the vertical dimension between source/drain patterns and field insulating films, transitioning from a planar layout to a three-dimensional structure. This vertical spacing effectively reduces capacitance without increasing horizontal pitch, thereby maintaining electrical stability while achieving high device density.
Solution Approach 2:
The patent introduces air gaps as intermediary spaces between conductive elements (source/drain patterns) and field insulating films. These air gaps act as mediators that reduce capacitive coupling between adjacent structures, enabling electrical stability to be maintained even when pitch size is reduced for higher density.
2Reliability
If gate length is increased to improve current control capability, then current control is improved, but device area increases
Solution Approach 1:
The patent utilizes vertical air gaps to enhance current control capability without extending the horizontal gate length. By controlling the electric field distribution in the vertical dimension through the air gaps, the device achieves improved current control while maintaining a compact footprint.
Solution Approach 2:
The patent applies air gaps selectively at specific locations (between source/drain patterns and field insulating films) to enhance current control capability locally. This localized approach improves current control without requiring a uniform increase in gate length across the entire device, thereby avoiding area expansion.
3Ease of manufacture
If conventional source/drain structures are used without air gaps, then manufacturing is simpler, but capacitance is higher and electrical stability is reduced
Solution Approach 1:
The patent incorporates air gaps during the formation process of source/drain patterns, performing the spacing action preliminarily before subsequent manufacturing steps. This preliminary introduction of air gaps ensures low capacitance and high electrical stability are built into the structure from the beginning, without requiring complex additional processing steps later.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device including first fin-shaped patterns in a first region of a substrate and spaced apart from each other in a first direction, second fin-shaped patterns in a second region of the substrate and spaced apart from each other in a second direction, a first field insulating film on the substrate and covering sidewalls of the first fin-shaped patterns, a second field insulating film on the substrate and covering sidewalls of the second fin-shaped patterns, a first source/drain pattern on the first field insulating film, connected to the first fin-shaped patterns, and including a first silicon-germanium pattern, and a second source/drain pattern on the second field insulating film, connected to the second fin-shaped patterns, and including a second silicon-germanium pattern, the second source/drain pattern and the second field insulating film defining one or more first air gaps therebetween may be provided.