FinFET Gate Spacer Air Gaps for Lower Parasitic Capacitance
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Solution Overview
Problem
The scaling of planar transistors is hindered by increasing limitations in processing capabilities and material characteristics, such as leakage current and process variations, prompting the need for non-planar transistors like FinFETs, where parasitic capacitance through gate spacers degrades performance due to high dielectric constants, and existing methods to reduce capacitance by forming air gaps can damage source/drain structures during etching.
Innovation Solution
The method involves forming a gate spacer with an air gap by patterning sacrificial gate spacers to block etchants, using top gate spacers as 'protection gate spacers' to prevent damage to source/drain structures during the formation of air gaps, thereby reducing parasitic capacitance and maintaining device integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If air gaps are formed by removing gate spacers to reduce parasitic capacitance, then parasitic capacitance is reduced, but source/drain structures are damaged during etching
Solution Approach 1:
The gate spacer is divided into two distinct parts: a sacrificial gate spacer that is selectively removed to form the air gap, and a remaining gate spacer that stays to protect the source/drain structures. This segmentation allows the etching process to create the desired air gap while the remaining spacer acts as a protective barrier, preventing etchant damage to the source/drain regions.
Solution Approach 2:
The remaining gate spacer serves as an intermediary protective element between the etchant and the source/drain structures. By positioning this spacer strategically, it mediates the interaction between the harmful etchant and the vulnerable source/drain regions, allowing the air gap formation process to proceed without damaging the critical source/drain structures.
2Strength
If continuous gate spacers are used to maintain device structure, then structural integrity is maintained, but parasitic capacitance increases due to high dielectric constant
Solution Approach 1:
The gate spacer is segmented into sacrificial and remaining portions, allowing selective removal of only the portion needed for air gap formation. This maintains structural integrity in the regions where spacers are retained while creating low-capacitance air gaps in critical regions, thus balancing structural strength with reduced parasitic capacitance.
Solution Approach 2:
Different regions of the gate spacer structure are assigned different qualities: the sacrificial portion is designed for selective removal to create air gaps where low capacitance is critical, while the remaining portion maintains structural support where mechanical integrity is prioritized. This local differentiation optimizes both structural strength and electrical performance.
Data Source
AI summary
A semiconductor device includes a channel structure, extending along a first lateral direction, that is disposed over a substrate. The semiconductor device includes a gate structure, extending along a second lateral direction perpendicular to the first lateral direction, that straddles the channel structure. The semiconductor device includes an epitaxial structure, coupled to the channel structure, that is disposed next to the gate structure. The semiconductor device includes a first gate spacer and a second gate spacer each comprising a first portion disposed between the gate structure and the epitaxial structure along the first lateral direction. The semiconductor device includes an air gap interposed between the first portion of the first gate spacer and the first portion of the second gate spacer. The air gap exposes a second portion of the first gate spacer that extends in the first lateral direction.