FinFET Air-Gap Spacer Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Aggressive scaling down of IC dimensions in FinFETs has led to increased parasitic capacitance, degrading device performance due to enhanced contributions from sidewall spacers, which existing techniques have not adequately addressed.
Innovation Solution
The introduction of air gaps as extremely low-k spacers between conductive features, such as gate structures, source/drain contacts, and their vias, to reduce parasitic capacitance and enhance device speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric spacers are used in FinFET structures, then manufacturing is simpler, but parasitic capacitance increases and device performance degrades
Solution Approach 1:
The patent changes the dielectric constant parameter of the spacer material from conventional values (k≈3-4) to air gap (k≈1.0), dramatically reducing parasitic capacitance. This parameter change directly addresses the technical contradiction by improving device performance through lower parasitic capacitance while accepting increased manufacturing complexity.
Solution Approach 2:
The patent employs a composite structure combining air gaps with conformal dielectric layers (e.g., silicon nitride, silicon oxide) to create hybrid spacers. This composite approach reduces parasitic capacitance compared to solid dielectrics while providing manufacturing control and structural integrity, partially resolving the contradiction between performance and complexity.
2Productivity
If IC dimensions are scaled down aggressively, then production efficiency improves and costs decrease, but parasitic capacitance increases and device performance degrades
Solution Approach 1:
By changing the spacer dielectric constant parameter to air gap (k≈1.0), the patent enables continued IC scaling while maintaining device performance. The low-k air gaps compensate for the increased parasitic capacitance that naturally occurs with smaller dimensions, allowing production efficiency gains from scaling without sacrificing device performance.
Solution Approach 2:
The patent converts the harmful effect of increased parasitic capacitance (which naturally occurs with scaling) into a benefit by using air gaps to create ultra-low-k regions. The scaling-induced proximity of features, which normally increases capacitance, is turned into an opportunity to maximize the benefit of air gap insulation where it is most needed.
3Speed
If air gaps are introduced to reduce parasitic capacitance, then device speed improves, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary actions by forming sacrificial spacer materials and mandrels before creating the final air gap structures. These preliminary structures guide the subsequent air gap formation process, ensuring precise placement and dimensions while simplifying the overall manufacturing sequence despite the added complexity of air gap creation.
Solution Approach 2:
The patent uses intermediary materials such as sacrificial spacers (e.g., silicon nitride, silicon oxide) and conformal dielectric layers that mediate between the manufacturing process and the final air gap structure. These intermediaries enable controlled air gap formation through selective removal or decomposition, making the complex air gap manufacturing process more manageable and precise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of air gaps significantly reduces parasitic capacitance, thereby improving the speed and performance of semiconductor devices by providing a lower dielectric constant and allowing for more efficient current flow and routing design flexibility.
Implementation Method 1
The introduction of air gaps as extremely low-k spacers between conductive features, such as gate structures, source/drain contacts, and their vias, to reduce parasitic capacitance
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.