FinFET Air Spacer Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As integrated circuit devices undergo down-scaling, there is a need to improve reliability by reducing unwanted parasitic capacitance while maintaining a reduced device area.
Innovation Solution
The integration of a fin-type active area with a gate line and an insulating spacer structure that includes an air spacer, which reduces parasitic capacitance by spacing nanosheets and conductive regions, thereby enhancing the reliability of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If down-scaling is applied to reduce device area, then device area is reduced, but parasitic capacitance increases and reliability deteriorates
Solution Approach 1:
The patent introduces air spacers that create air gaps (porous structure) between conductive regions such as the gate electrode and source/drain electrodes. These air gaps act as low-dielectric-constant regions that reduce parasitic capacitance formed between adjacent conductive structures in the scaled-down device, thereby maintaining reliability despite reduced device area.
2Reliability
If conductive areas are reduced to lower parasitic capacitance, then parasitic capacitance is reduced, but device functionality may be compromised
Solution Approach 1:
The air spacer acts as an intermediary structure positioned between conductive regions. It provides electrical isolation and reduces capacitive coupling without requiring changes to the fundamental conductive pathways, thus maintaining device functionality while reducing parasitic capacitance effects.
Solution Approach 2:
The patent changes the dielectric parameter between conductive structures by introducing air gaps with low dielectric constant. This parameter change reduces the capacitance value (C = εA/d) between adjacent conductive regions without altering the conductive areas themselves, preserving functionality while reducing parasitic effects.
3Reliability
If air spacers are introduced to reduce parasitic capacitance, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The air spacer formation process is merged with the existing spacer formation工艺流程. The air spacer is formed by removing a sacrificial material from a pre-formed spacer structure, combining multiple functions (isolation, capacitance reduction) into a single integrated structure that follows existing manufacturing flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance, improving the ON and OFF current characteristics of transistors, leading to enhanced performance and reliability of integrated circuit devices.
Implementation Method 1
it is necessary to secure not only a fast operation speed but also an operation accuracy in an integrated circuit device. Accordingly, there is a need to develop a technology for an integrated circuit device capable of improving reliability by reducing an unwanted parasitic capacitance
Data Source
AI summary
An integrated circuit device includes a fin-type active area extending in a first horizontal direction on a substrate, a channel area on the fin-type active area, a gate line surrounding the channel area on the fin-type active area and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer structure covering gate sidewalls of the gate line and channel sidewalls of the channel area, wherein the insulating spacer structure includes an air spacer having a first portion facing the gate sidewalls in the first horizontal direction and a second portion facing the channel sidewalls in the second horizontal direction.