FinFET Airgap Spacer Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices continue to shrink, parasitic capacitance and off-state leakage become significant issues, necessitating improvements in transistor design and fabrication to reduce these negative effects while maintaining performance.
Innovation Solution
The introduction of airgaps within the semiconductor structure by recessing a high-k dielectric layer in the gate structure, which reduces the effective dielectric constant and improves effective capacitance (Ceff) of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If transistor size is reduced to achieve greater circuit density, then device size decreases, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the harmful high-k dielectric material from the gate structure and replaces it with an airgap (vacuum). By removing the high-k material that contributes to parasitic capacitance and replacing it with air (which has a dielectric constant of approximately 1), the parasitic capacitance is significantly reduced while maintaining the compact device structure
Solution Approach 2:
The patent changes the dielectric constant parameter of the gate structure by replacing high-k material (dielectric constant > 3.9) with airgap (dielectric constant ≈ 1). This parameter change directly reduces the parasitic capacitance between the gate and source/drain regions, solving the problem of increased parasitic capacitance in scaled devices
2Volume of moving object
If transistor size is reduced to achieve greater circuit density, then device size decreases, but off-state leakage increases
Solution Approach 1:
The patent removes the high-k dielectric material from the gate structure and replaces it with an airgap. This extraction eliminates the source of parasitic capacitance that contributes to off-state leakage, thereby reducing the harmful leakage current in scaled transistors
3Power
If gate width is increased to improve drive current, then drive current increases, but transistor footprint increases
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate structure by introducing an airgap, which reduces parasitic capacitance. This allows the transistor to achieve higher drive current with a smaller footprint, as the reduced parasitic effects improve the effective drive capability without requiring larger dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The formation of airgaps effectively reduces parasitic capacitance and enhances the effective capacitance of the semiconductor device, addressing the challenges of device size reduction and performance maintenance.
Implementation Method 1
The airgap provides a reduced effective dielectric constant between the lateral side surfaces of the metal gate structure and the spacer layer
Data Source
AI summary
Embodiments of the disclosure advantageously provide semiconductor devices, fin field effect transistors (FinFETs) in particular, and methods of manufacturing such devices having improved effective capacitance (Ceff). The FinFETs include a gate structure in which airgaps are provided by recessing a high-k material layer disposed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high-k dielectric layer and improving effective capacitance (Ceff) of the device.