FinFET Alignment Mark Formation via Insulating Trench Fill

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Solution Overview

Problem

The challenge in manufacturing FinFET semiconductor devices lies in accurately forming alignment marks, as Chemical Mechanical Polishing (CMP) processes are difficult to control, leading to issues like dishing and smearing of insulating material, which can distort alignment marks and hinder proper alignment of structures during the fabrication of integrated circuits.

Innovation Solution

The method involves forming a plurality of spaced-apart fin structures in a semiconductor substrate to define an alignment/overlay mark trench, filling it with insulating material, and removing excess material to create a robust alignment/overlay mark, primarily composed of insulating material, which is more predictable and less prone to distortion during CMP processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional CMP processes are used to form alignment marks, then the alignment marks can be formed, but the insulating material becomes difficult to control leading to dishing and smearing that distort the alignment marks

Engineering Contradiction:

Improvealignment mark accuracyVSAvoidalignment mark integrity

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent extracts the alignment mark formation process from the problematic CMP process by using a self-aligned etch approach. Instead of forming alignment marks through CMP of insulating material, the method uses etched features in the substrate that automatically align with fin structures, eliminating the dishing and smearing issues associated with CMP while maintaining alignment accuracy.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent inverts the traditional approach by not forming alignment marks as separate insulating material features, but rather by creating alignment references through etched substrate features. This inversion eliminates the need for CMP processing of alignment mark material and avoids the associated distortion problems.

Inventive Principle:

Principle #13The other way round (Inversion)

2Ease of manufacture

If alignment marks are formed using insulating material, then they can be created, but the CMP process causes dishing and smearing that distorts the marks

Engineering Contradiction:

Improvealignment mark formationVSAvoidalignment mark shape accuracy

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent replaces the mechanical CMP process with a chemical etching process. Instead of mechanically polishing insulating material to form alignment marks, the method uses selective etching of the substrate to create alignment features, eliminating the mechanical forces that cause dishing and smearing while maintaining ease of manufacture.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Speed

If the channel length of FETs is decreased to improve switching speed, then operating speed improves, but the separation between source and drain decreases causing short channel effects

Engineering Contradiction:

Improveswitching speedVSAvoiddevice operation characteristics

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent transitions from planar FET structures to three-dimensional FinFET structures. By extending the channel into the vertical dimension with fin-shaped active areas, the gate electrode can enclose multiple sides of the channel, providing better electrostatic control and reducing short channel effects even as the horizontal channel length is decreased for higher switching speed.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the accuracy and robustness of alignment marks, reducing the risk of distortion and improving the alignment process, thereby ensuring better operational efficiency of FinFET devices by maintaining the integrity of the alignment marks during the manufacturing of integrated circuits.

Implementation Method 1

Chemical Mechanical Polishing (CMP) processes are difficult to control, leading to issues like dishing and smearing of insulating material

Methodology Applied

Scientific EffectChemical Mechanical Polishing:

Data Source

PatentUS9275890B2Methods of forming alignment marks and overlay marks on integrated circuit products employing FinFET devices and the resulting alignment/overlay mark

Publication Date: 2016.03.01 KLA CORP

AI summary

One illustrative method disclosed herein includes forming a plurality of spaced-apart fin structures in a semiconductor substrate, wherein the fin structures define a portion of an alignment/overlay mark trench where at least a portion of an alignment/overlay mark will be formed, forming at least one layer of insulating material that overfills the alignment/overlay mark trench and removing excess portions of the layer of insulating material positioned above an upper surface of the plurality of fins to thereby define at least a portion of the alignment/overlay mark positioned within the alignment/overlay mark trench. A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to partially define an alignment/overlay mark trench, an alignment/overlay mark consisting only of at least one insulating material positioned within the alignment/overlay mark trench, and a plurality of FinFET semiconductor devices formed in and above the substrate.