FinFET Back Gate Conductor Well Region Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing power consumption and size while avoiding spontaneous heating effects and high costs associated with back gate formation in FinFETs, particularly due to small contact surface areas and expensive SOI wafers, as well as performance fluctuations from unintended doping.
Innovation Solution
A semiconductor device and manufacturing method that incorporates a back gate conductor adjacent to semiconductor fins with a well region as a conductive path, avoiding the need for ion implantation through the fin and thus preventing spontaneous heating and performance fluctuations, while maintaining control over threshold voltage and suppressing short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a back gate is formed in a FinFET based on a bulk semiconductor substrate, then power consumption can be reduced, but spontaneous heating effect occurs due to small contact surface area
Solution Approach 1:
The back gate conductor is extended into the well region laterally, increasing the contact surface area from a small point contact to an extended planar contact. This dimensional extension allows better heat dissipation while maintaining the back gate's power consumption reduction capability
Solution Approach 2:
The back gate conductor is segmented into multiple regions: a first region over the semiconductor fin and a second region extending into the well region. This segmentation allows different functional zones - one for electrical control and another for heat dissipation and conductive path formation
2Use of energy by moving object
If a back gate is formed in a FinFET based on an SOI wafer, then power consumption can be reduced, but manufacturing cost increases due to expensive SOI wafers
Solution Approach 1:
The invention replaces expensive SOI wafers with a bulk semiconductor substrate, using a cheaper material foundation. The back gate function is achieved through the well region structure rather than requiring costly pre-fabricated SOI layers
Solution Approach 2:
The well region serves multiple functions: it acts as the conductive path for the back gate, provides mechanical support, and enables standard bulk substrate processing. This multi-functionality eliminates the need for specialized SOI wafers while achieving the same electrical control benefits
3Reliability
If ion implantation is used to form a back gate in an SOI wafer, then a conductive path can be created, but device performance fluctuates due to unintended doping in the channel region
Solution Approach 1:
The invention extracts the back gate conductor formation from the ion implantation process. Instead of using ion implantation to create the conductive path, a separate back gate conductor is deposited and patterned, eliminating the harmful unintended doping in the channel region
Solution Approach 2:
The well region acts as an intermediary conductive path between the back gate conductor and the substrate. This intermediary structure provides the necessary electrical connection without requiring direct ion implantation through the channel region, thus preventing performance fluctuations
4Temperature
If the contact surface area of the semiconductor Fin and substrate is increased, then spontaneous heating effect is reduced, but device size increases
Solution Approach 1:
The back gate conductor extends laterally into the well region, increasing the contact surface area in the planar dimension rather than increasing the vertical footprint. This allows improved heat dissipation without proportionally increasing the overall device volume
Solution Approach 2:
The back gate conductor has different properties in different regions: in the first region it provides electrical control over the fin, while in the second region extending into the well it provides heat dissipation and conductive path functionality. This local differentiation optimizes both thermal and electrical performance without uniform size increase
Data Source
AI summary
High integrity, lower power consuming semiconductor devices and methods for manufacturing the same. The semiconductor device includes: semiconductor substrate; a well region in the semiconductor substrate; an interlayer structure over the well region, the interlayer structure including a back gate conductor, semiconductor fins at both sides of the back gate conductor and respective back gate dielectric isolating the back gate conductor from the semiconductor fins, respectively, wherein the well region functions as one portion of a conductive path of the back gate conductor; a punch-through stop layer at a lower portion of the semiconductor fin; a front gate stack intersecting the semiconductor fin, the front gate stack including a front gate dielectric and a front gate conductor and the front gate dielectric isolating the front gate conductor from the semiconductor fin; and a source region and a drain region connected to a channel region provided by the semiconductor fin.